FIFO Overflow and Underflow

S

sysysy

New Member

• May 6, 2012

• #1

Hi,

recently i read the altera articles about the FIFO.

My question is regarding the fifo overflow and underflow,
May i know overflow happen when the fifo is already full?
for example, the read clock is slower than the write clock.

underflow mean the fifo is already empty?
for example, the write clock is slower than the read clock.

is my concept correct or not?
else, what is the overflow and underflow means in a fifo?

thanks

 

K

kubeek

Well-Known Member

Most Helpful Member

• May 6, 2012

• #2

Yes that is exactly what overflow and underflow means in buffers. For LIFO it is the same.

 

S

sysysy

New Member

• May 6, 2012

• #3

Thanks for the reply.

Besides, the article also mentioned about 0ppm (part per millions)
I try to google about the ppm! PPM is used in many aspects...

may i know what is exactly ppm means in the frequency?
Again, for my own understanding, i assume 0 ppm means there is no phase compensation btw 2 clocks?

For example, the rising edge of clk1 and clk2 must be in phase or align?

 

Mikebits

Well-Known Member

• May 6, 2012

• #4

Yeah PPM is confusing, an instructor once told me, if one person farts in a crowd of 1 million, you have 1 fart PPM.

 

K

kubeek

Well-Known Member

Most Helpful Member

• May 6, 2012

• #5

PPM is a relative value, the same way you have 1% which is one part per hundred, you have 1PPM which is one part per milion. So if you´re talking about accuracy, then 1ppm accuracy is equal to 0.0001%.
I don´t see how it relates to two clock sources and the phase of their edges, could you post some link to where that is mentioned?

 

S

sysysy

New Member

• May 6, 2012

• #6

Here is the link:
**broken link removed**

Volume 2, chapter 1 --> page 32/520 (pdf format)
Table 1- 7 (Bonded Functional)

 

K

kubeek

Well-Known Member

Most Helpful Member

• May 6, 2012

• #7

It looks like you have to set some setting to get the clocks matched, but I cant really make heads or tails of it.