Forbidden region of CMOS invertor

[tech_vaibhav_eee]

Hi,
I know the basic working of a CMOS invertor. what I don't understand is how it works in the forbidden region. I'll ask my doubt with help of an example.

(W/L)p=5*(W/L)n
Un=3Up(pronounce U=myu)
Vthn=0.7v=|Vthp|
Vdd=5v
Suppose at present my invertor output is 0v. I give a input voltage of 2.7v. What will be the value to which my output will settle.
Repeat the same question with input=0.8v(the difference it will create is that the pmos will be initially in the linear region now.)

From what I understand,since both the transistors are out of cutoff , in any of the case , pmos will try to charge the capacitor to 5v while the nmos will try to discharge it to 0v. So, I believe that the output will be 0v if the resistance of nmos is less than that of pmos and the output will remain at 5v otherwise.
But, the resistance of a mosfet is not constant but varies with the current.
Also, voltage characterstics of a invertor shows that of intermediate values such as 2.7v, the output is not 0v or 5v , but actually lies somewhere in between.
So, basically I am confused. Can anybody help?

PS:This is no homework question. And I read a lot of books before asking this question. The problem is, no book covers this topic.

Thanx in advance!!

 

[Grossel]

It heavilly depends on what hangs on the output and each transistors characteristics.

It has being some time since I had this on school, so it would be easier if you uploaded a drawing for reference.

 

[crutschow]

If the input is at or below the low level logic threshold, then the input will be at a logic low and the output will at 5V. If the input is at or above the high level logic threshold, then the output will be 0V. Anywhere in between those two input levels, the output is indeterminate and can be anywhere from 0V to 5V. This will vary due to manufacturing differences from one gate to the next.

 

[MikeMl]

I'm confused about your terminology. Are you asking about what happens as the input of a CMOS inverter is slowly ramped from Vss to Vdd?

There will be a region somewhere where both the PMOS and NMOS are partially turned on, so the output will be in an indeterminate logic state, where there will be substantial "shoot through" power-supply current flowing through the two series devices. Without very detailed process parameters, and accurate Spice models, that is all anyone can say about it.

 

[Roff]

Google "cmos inverter transfer characteristic".

 

[audioguru]

There is CD4xxx "ordinary" Cmos logic and there is 74HCxxxx "high speed" Cmos logic.
When the supply is 5V then their input switching voltage threshold is from 1.5V to 3.5V. The switching voltage threshold tor 74HCTxxxx is different.

When a CD4xxx is linear then the supply current is about 3mA which is fairly low.
When a 74HCxxxx is linear then the supply current is about 48mA which is high enough to destroy it if it is continuous.

 

[tech_vaibhav_eee]

Thanx for all the replies.

I didn't mean that the input will be slowly ramped from Vdd to Vss or vice-versa. I believe in that case, the output will not remain constant but will follow the VTC.
What I meant was that the input be kept stable at some voltage within the forbidden region. I now understand that in such a case , I will have to consider that which transistor is in which region at the time and equate the current equations for both PUP & PDN network. But this quantitative approach is cumbursome . So, I believe that if I plot the VTC of the invertor using PSpice , I can get values of output voltages for corresponding Input voltages by just getting x and y coordinates on that plot.

 

[audioguru]

But don't you understand that the threshold voltage where the inverter switches is a wide range of voltages because the inverters are not all the same?

With a 5.0V supply the output might be linear (the N-channel Mosfet and the P-channel Mosfet are both turned on) when the input voltage is 1.5V, 2.0V. 2,5V, 3.0V or 3.5V.

I measured some CD4069 inverters ICs and the threshold voltage on all of them was not 2.5V.
PSpice would show only a 2.5V "perfect" one.