The issues with starting with programmable logic (CPLD's, FLGAs etc..) is usually the IDE software is massive, and can be extremely complicated. For example, Altera's Quartus II, last time I checked, was a 2.8Gig install. Xilinx has a similar sized IDE software, although you can choose which dfeatures to install, so if you don't use $400 Vertex III's fpga's, then no need to install the software parts for them.
Then theres design entry. At the most basic level, theres schematic. Manually adding gates and registers. Thers generally two HDL's (hardware description languages), Verilog: C-style syntax, quite forgiving. And VHDL: another standard, which I dont' get on with, but some say is more flexible. Theres a more basic language, ABEL, used by Lattice and Xilinx, but is only supported for small CPLD's.
Once you have a design, you have to fit it, optimised it: tell the software if you want speed, or 'resource' optimisation, as well as decide what pins on the device are connected to what. Each pin can have a number of parameters....drive level, logic standard... slew rate. So it can be extremely daunting at first.
That said, a good tutorial is always handy. You also learn what 'default settings' are appropriate for all your projects. Only 'playing with settings' when you actually need them. Example: Changing the slew-rate of pins when you design your first 2GB/s LVDS link
So, once over the 'hump', almost all the settings and parameters are the same, and you're just left with writing your design and 'going through the motions' of msetting things up.
One can't relaly compare FPGA's to CPU's/microcontrollers, since uC's have fixed hardware. Micro's interpret instructions, and run the hardware based on that. FPGA's are about configuring a chip to BE hardware. Which means you have to write a lot more 'code' (its not really code) to instruct the FPGA to be a simple 8-bit counter, or an 8-input XOR gate.
That said, its real beauty lies in its modular design. I often write 'blocks' that do certain functions, then link them together in a high-level schematic. These can always be reused in other designs, and so you build up a library of useful and ever increasingly complicated 'blocks'. Similar to 'includes' in C code but perhaps more versitile, since it is not restricted to a certain processor, with certain registers. Providing your FPGA has enough resources (slices/logic blacks/registers) ANY verilog/VHDL design will run on it. Meaning with the oprncore.org community, you can plug things together with a bit of glue logic to make some really impressive and high speed designs.
There are some lovely cheap FPGA dev boards around, along with onboard 'download cables', and breakout boards which are a good way to go for starting. In fact, I went from CPLD's to a cycloneII FPGA, and I have yet to reach the 'limit' on resources, despite trying..... that was only $30 from ebay.
Good luck!