FPGA LED Help w/ Verilog

Status
Not open for further replies.
Good job! I suggest that instead of relaxing the constraints, you just eliminate the offset. I don't think it's needed anyway. But if you're relaxing the clock period, you might get a design that doesn't work. At least in the future, your clock period should reflect the actual clock being used.
 
Status
Not open for further replies.
Cookies are required to use this site. You must accept them to continue using the site. Learn more…