I think that you mean that the 4059 is overkill. There's nothing wrong with overkill. None of the solutions suggested use all the functions of all the ICs, so all of them have some overkill.
There could be an issue with the ripple counter. A solution is an RC filter on the output of the AND gate, so that the output is delayed by a bit longer than the possible length of a false pulse, but still much faster than the shortest pulse length.
There is a variation of the scheme with the 7490 that gets over that problem.
If you connect the clock input to ClkB, then QB, QC and QD will divide by 5. If you connect QC and ClkB to the two R9 inputs (pins 8 and 1) then that will divide by 3 with no danger of a race condition.
The count starts at 4 on the divide by 5 part when reset. (QD = 1)
The next high to low transition makes the output go to 0
The next high to low transition makes the output go to 1 (QB = 1)
The next high to low transition makes the output go to 2 (QC = 1)
The next low to high transition means that Clk and QC are both 1, so the counter is reset to 4 again.