Here's an alternative design, which (in simulation at least!) accepts various input duty cycles and pulse shapes, gives a 50% output duty cycle and enables adjustment of the ratio of the output and input frequencies (including non-integer ratios). I set myself the challenge of using a single IC, so the design is somewhat unusual
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U1 is a hex inverter.
U1a,U1b,R1,R2 are configured as a Schmitt trigger inverter. Q1,Q2 ,Q3 provide a controlled current for charging/discharging C1, and together with the Schmitt inverter form a VCO whose frequency is controlled by the voltage on C2.
The VCO output drives a 'pseudo-monostable' Mono1 (C3,R6,U1d) to give fixed-width brief pulses which, via D2, act to pull down the top end of the pot and hence discharge C5.
The input pulses from the VSS trigger a true monostable circuit Mono2 (U1e,U1f,C4,R7,R8,D4) which outputs brief pulses having the same fixed width as those from Mono1 and which, via D3, act to pull up the bottom end of the pot and hence charge C5.
The pot sets the relative weighting of the pull up and pull down effects and hence the integrated mean voltage on C5. When this voltage crosses the threshold of U1c the gate output flips. U1c output is smoothed by R5,C2 to give the VCO control voltage. By virtue of this feedback, the voltage on C5 stabilises at close to the switching threshold of U1c, i.e. at about Vdd/2, and VCO frequency /VSS Input frequency is set by the pot.
Edit:
The width of the fixed-width pulses might need to be tweaked according to the number of teeth on the reluctor wheel of the VSS.
Edit2:
The time constants R(pot)C5 and R5C2 will need tweaking depending on the input and output frequencies.