Full Audio Spectrum Sinewave Generator using DDS

By using Direct Digital Synthesis (DDS), what could be the block diagram of a sinewave generator which covers the frequencies of the audio spectrum from 20 to 20,000 Hz (3 decades)?

The basic block diagram could be:
MCU programmed to run the sinewave DDS loop.
R2R ladder connected to 5, 6, 7 or 8-pin port of the MCU.
Active low pass filter which works also as a buffer connected to the R2R output.

The question (homework) is:
Is it possible for one active LPF of a certain cutoff Fo, at the output of the R2R ladder, to cover the full audio spectrum?
If not, what could be the solution (as a block diagram)?

Truth be said, I gave this homework to myself this morning
Although I doubt that a reader here could be interested in solving it, perhaps someone will surprise me by finding a practical solution before I do

Have fun,
Kerim

This is one, single chip approach :



Another (4 channel single chip) :



Its arbitrary waveform. Using onboard DMA to drive WaveDAC8 from DDS. Again single chip, lots of
resources left for other tasks, like SAR, DelSig, DSP Filter, Logic, .......Could use COM to manage, like USBUART
or I2C or SPI, also onchip.

Other stuff onchip (many multiple copies), all with extensive API f() libraries to manipulate each component :



Note here is a different application (burst N cycles of an arbitrary waveform) :



Regards, Dana.

Take a look at this for table size versus distortion :


Note the dev board to do this is $ 15 : https://www.infineon.com/cms/en/product/evaluation-boards/cy8ckit-059/



Regards, Dana.

Simulate it and run an FFT on the output and you will have your answer.

Thank you Dana.

By the way, the variable audio generator I am referring to is the one which can generate sinewaves in steps (not more than 1.1% step) with a relatively low THD from 20 Hz to 20,000 Hz.
In other words, when the MCU receives an index number, say from 0 to 967, it generates the indexed frequency as on the text table attached, for example.

The reason for which I gave myself this homework is that I used another algorithm to synthesize sinewaves by using a serial DAC (using basic delta modulation) instead of the parallel one (DDS). The new topology could be called Delta Sinewave Synthersis (DSS).
DSS outputs, therefore, the sinewave bit stream from one MCU pin only. But, for relatively high frequencies, DSS code uses internally all 8 bits of a port (though one of them only outputs the delta serial bits).
The only DSS advantage is that its hardware is simple while covering a relatively wide band of frequencies (in my design, from 20,000 down to 630 Hz, the high band, and 630 down to 20 Hz, the low band) while maintaining a practical low THD. The active LPF filter (of a 3rd order) which is used for the high band is also used for the low band as well by adding 3 capacitors to it. They are switched in parallel with the original ones by 3 CD4066 switches that are controlled by one MCU pin.

The disadvantage of DSS is that its code is not trivial (mainly for the high band). This is why I didn’t hear that someone worked on it yet. And, to let DSS to cover a wider band with the same LPF, the needed MCU memory space increases somehow exponentially. Also, it is somehow a challenge to choose/find the tables of the delta bit streams which output the same signal amplitude for all generated frequencies.

For instance, I have, as MCU, just the ATmega8A to which I usually add an 8 MHz crystal (though I can use a 16 MHz one, if necessary).
So, before going on working on DSS project to build the variable audio sinewave generator, I thought that, also by using a relatively simple hardware (no special ICs or precise components which could be used in simulators), I may be able doing it by using the much simpler DDS code and look-up table(s). I still wonder if this is possible to be achieved with DDS.

I hope now that the purpose of homework here is clear

Thank you,
Kerim

During my study of DDS, I noticed that, in general, DDS generates sinewaves with frequency jitter.
In case the main counter is 16-bit and the incrementing step is 16-bit, if step is of the form 2^x, we can get a specific (not average) frequency. This applies on DDS 7-clock loop (its sinewave 256-byte table is moved to SRAM).
A DDS 9-clock loop can reset the main counter to a certain initial value every time a sample from the sinewave table is read. This also gives a desired frequency without jitter.

In general, DSS generates the sinewaves without frequency jitter. The worst case happens when the number of the delta bits in one cycle is odd. In this case, the average frequency is of two consecutive cycles.