R rds1975 New Member Sep 20, 2004 #1 Can some one tell me to generate a gate level logic circuit for the below one. Iam trying to solve myself and just want to verify. A B C Z 0 0 0 1 0 0 1 0 0 1 0 0 0 1 1 1 1 0 0 0 1 0 1 1 1 1 0 1 1 1 1 0 Thanks
Can some one tell me to generate a gate level logic circuit for the below one. Iam trying to solve myself and just want to verify. A B C Z 0 0 0 1 0 0 1 0 0 1 0 0 0 1 1 1 1 0 0 0 1 0 1 1 1 1 0 1 1 1 1 0 Thanks
A alamy New Member Sep 22, 2004 #2 u can use karnaugh map or quine mccluskey method to simplify ur boolean...there are few software on net for the purpose method...
u can use karnaugh map or quine mccluskey method to simplify ur boolean...there are few software on net for the purpose method...
williB New Member Sep 22, 2004 #3 it looks like it is as follows. ABC' + AB'C + A'B'C' +A'BC you can implement it with three inverters and four 3 input AND gates all ORd together. or You can use an exclusive OR gate on A & B send this to an equivilence gate with C. or strangely enough You can equivilence A & B and Exclusive OR the output with C.
it looks like it is as follows. ABC' + AB'C + A'B'C' +A'BC you can implement it with three inverters and four 3 input AND gates all ORd together. or You can use an exclusive OR gate on A & B send this to an equivilence gate with C. or strangely enough You can equivilence A & B and Exclusive OR the output with C.
bonxer New Member Sep 23, 2004 #4 You could also consider that to be an B exclusive-OR C, being inverted by A.