The article says that the divider current should be 10 times the typical base current. The total resistance of your divider is 253k.
Their current is only 59.3uA
They create an unloaded voltage of 1.96V for the base of the transistor.
The transistor loads down the voltage divider so its voltage will be about 1.67V and the emitter of the transistor will be about 1.02V and its current will be 3.78mA.
The typical curent gain of the transistor is about 200 so its base current is about 18.9uA. The values of the divider should have a total resistance of 79.4k ohms, not 253k ohms.
Sorry but that doesn't explain why it isn't acceptable for the resistance to be that high.
Is it due to the stability of the transistor?
I simulated the circuit with an Hfe of 100, the Vc = 7.3V, I reduced the gain to 50 and it was 9.87, I increased it to 400 and it was 2.5V.
Reducing the potential divider resistance will make the bias voltages more stable. Using the values you say will mean Vc will vary between 9.75V and 6.9V when the Hfe is varied from 50 to 400.
So having a lower resistance potential divider reduces the effect of loading by the transistor so the bias voltage will change less.
That makes sense but what if the voltage swing is just 1V?
Fair enough I can see that being a problem for the second stage where the voltage swing will be quite large but who cares if the bias varies widely on the first stage?
The voltage swing will be under 1V so it doesn't matter.
See the revised schematic.
The first stage uses higher value resistors to provide a higher input impedance. The voltage swing is tiny because the gain is low.
The second stage has lower value resistors in the potential divider to make it more stable.
It works just as well when the Hfe is 50 or 500.