Help designing dual H-bridge controller

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chadj2

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I am trying to build a circuit to control 2 H-bridges. The H-bridges outputs must be 90 degrees out of phase with each other. I was thinking about using a sg3524 signal to control one H-Bridge and using the same signal as an input to 2 556 timers acting as a delay and trigger signal to the other H-bridge. I don't believe I have the skills to use a microcontroller unless I am thinking it is more complicated than it is. If anyone has any ideas as to how I can control this setup more effectively please give me some guidance.

Chad
 
You can get the 90 degree phase shift, complete with true and complement outputs which you will probably need for your H-bridge, with a 2 stage Johnson counter.
 

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Thank you so much for the suggestion Roff. I need to study this counter further. I do have one concern with this counter at first glance. I am not sure how I would get the dead time that may be needed so that the transistors dont accidently dead short to each other during on/off transistion.
 
Have a look at the Intersil range of MOSFET drivers - they do some that are full/half bridge and you can use N-Channel Mosfets for both the high and low side. They also have adjustable delay between turn on and turn off of the pairs of transistors.

www.intersil.com
 

To add a dead time, put 2 (or 4) NAND gates between the flip flop's outputs (Q1, notQ1, Q2 and notQ2) and the H bridge.

Use a clock with a low duty cycle (ie tON = 5% of the period) and connect the second input of eact gate to the clock.

This way while the clock is up (5% of the period) the four outputs will be low, and the remaining 95 % of the period the outputs will drive the bridge.
 
I know that is sometimes an issue. You would either need to add some more logic, or just use a PIC.
 
You can get the dead time with a couple of latches, as below. Each delay element (if needed for additional dead time) can be an even number of inverters and/or an RC network.
 

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Thanks again for the idea Ron. I think I will go with the RC network with a PNP and asymetrical charge discharge path.

Chad
 
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