please help me with the following coding...
for(j=0; j<10; j++)
{
for(i=0; i<5; i++)
{
A <= D;
A = A+4;
}
A = A + 10;
}
D value changes for every change in A.... it will be given externally..... D will be different for diffent A... how can i implement this in vhdl.... i am using xilinx 6.1 n modelsim to see d output.... also tel me how can i see the out put...
thanks a lot...
with regards...
for(j=0; j<10; j++)
{
for(i=0; i<5; i++)
{
A <= D;
A = A+4;
}
A = A + 10;
}
D value changes for every change in A.... it will be given externally..... D will be different for diffent A... how can i implement this in vhdl.... i am using xilinx 6.1 n modelsim to see d output.... also tel me how can i see the out put...
thanks a lot...
with regards...