I am given task:
Design an octal-to-7-segment common cathode decoder for digits 0 to 5 only using the least possible number of basic gates (i.e. an optimum design). The 7-segment will only need to display from octal digits 0 to 5, ignore other numbers Your solutions must show all the design steps taken, i.e. a description of the task, requirements definition, design approaches such as truth-table(s), simplification using K-maps or Boolean theorems, and the implementation (circuit diagrams) using standard logic symbols.
I have come out with the truth table. But I'm clueless about the basic gates needed, simplification using K-maps or Boolean theorem,
3 switches name A, B, C.
so when the switches are:
* A=off/0 B=off/0 C=off/0 *, the display will be 0
* A=off/0 B=off/0 C=on/1 *, the display will be 1
* A=off/0 B=on/1 C=off/0 *, the display will be 2
* A=off/0 B=on/1 C=on/1 *, the display will be 3
* A=on/1 B=off/0 C=off/0 *, the display will be 4
* A=on/1 B=off/0 C=on/1 *, the display will be 5
Would REALLY REALLY appreciate if anyone can help.