CMOS logic dissipates more power as the frequency increases for two reasons. One is "shoot-through" current, and the other is due to the fact that it will always have a capacitive load that has to be charged and discharged at the switching frequency.
The shoot-thru current is caused by the fact that the pullup (Pchan) and pulldown (Nchan) transistors are on simultaneously during the transition between logic levels. This can possibly be alleviated somewhat by clever circuit design, probably at the expense of propagation delay.
The capacitor charging power cannot be eliminated. The capacitance is the sum of device output capacitance, package parasitic capacitance, wiring capacitance, and the capacitance of any devices which are being driven. The power dissipated by the logic device driving this capacitance is
P = F*C*V^2
Where F is the switching frequency, C is the aforementioned capacitance, and V is the supply voltage of the CMOS logic device.
Having explained all this, I gotta say I'm not sure this this addresses your question. :roll: Does it? What problem are you trying to solve?