You can write functions in VHDL (in a package).
There is only one problem.
Their only use in synthesis is to generate constant values. Under simulation (test bench), you can write typical "computer" code. Under synthesis, you are highly restricted in the code you can write.
So far, you have been using the fundamentals of software - sequences, iterations, and alternatives.
However, the fundamentals of sequential digital hardware are quite different. One possible set of fundamentals include: selection (multiplexing of several inputs into one output), distribution (connecting one output to one or more inputs), and updating (register clocking under control signals).