Help...Problem while using while loop inside a case...

[mackrants]

[VHDL] - Problem while using while loop inside a case.need help..

Hi,

I am working with Quartus II on an cyclon 1 altera device.
My programming language is VHDL.

I am trying to write a Sync Decoder that recognize when the data_in pin input is "111000" - serial input.


Here is my code:

Library ieee;
use ieee.std_logic_1164.all;
Entity Decoder is


	port(
		d_in: in std_logic;
		clk: in std_logic;
		d_out: out std_logic_vector(31 downto 0)
		);
end entity;	
architecture behave of Decoder is


TYPE state_type is (sync_detecting,decoding);
signal state:state_type;
CONSTANT SYNC : std_logic_vector := "111000";
signal i : integer range 0 to 6;
BEGIN

process(clk,d_in)
variable sync_detected_n : std_logic;

Begin

if rising_edge(clk) then
	case state is 
		when sync_detecting =>
				sync_detected_n := '1';
				i<=0;
				sync_detection : while i<5 loop 
					if rising_edge(clk) then
							
						if d_in = SYNC(i) then
							i<=6;
						else 
							i<=i+1;
						end if;
							
						if i=5 and d_in<=SYNC(i) then
							sync_detected_n := '0';
						end if;
					end if;
					exit sync_detection when i<=1;
				end loop;
						
						if sync_detected_n = '1' then
							state<= sync_detecting;
						else
							state<= decoding;
						end if;
		When decoding=>
			d_out<="11111111111111111111111111111111";
	end case;
end if;
end process;
end;

I get the Error (10536): VHDL Loop Statement error at manchester_encoder.vhd(31): loop must terminate within 10,000 iterations.

Can someone explain to me why I cant compile this file?


I want to program it into a cyclone I processor.

10x alot,
Asaf

 

[vne147]

I can't help you because I don't know the language you are using but I have some suggestions that might help you get help from the right people.

First off all, this question is probably more suited for the micro controller forum here.

Second, it's better to put your code into code brackets like this:

Library ieee;
use ieee.std_logic_1164.all;
Entity Decoder is


port(
d_in: in std_logic;
clk: in std_logic;
d_out: out std_logic_vector(31 downto 0)
);
end entity; 
architecture behave of Decoder is


TYPE state_type is (sync_detecting,decoding);
signal state:state_type;
CONSTANT SYNC : std_logic_vector := "111000";
signal i : integer range 0 to 6;
BEGIN

process(clk,d_in)
variable sync_detected_n : std_logic;

Begin

if rising_edge(clk) then
case state is 
when sync_detecting =>
sync_detected_n := '1';
i<=0;
sync_detection : while i<5 loop 
if rising_edge(clk) then

if d_in = SYNC(i) then
i<=6;
else 
i<=i+1;
end if;

if i=5 and d_in<=SYNC(i) then
sync_detected_n := '0';
end if;
end if;
exit sync_detection when i<=1;
end loop;

if sync_detected_n = '1' then
state<= sync_detecting;
else
state<= decoding;
end if;
When decoding=>
d_out<="11111111111111111111111111111111";
end case;
end if;
end process;
end;

Third, the more details you provide, the less people are going to have to search through your code and figure things out for themselves and the more help you will recieve.

Some details that might be helpful in this case are, what programming language are you using? What compiler are you using? What is the program supposed to do? What is the line number of the loop that's causing the compiler error. Just try to think what you would need to know if you were trying ot help someone else and include that information.

Good luck and I hope you find someone who can help.

 

[mackrants]

10q very much..
I'v changed it.
I hope you can figure it out now and help me please...

thanks alot again!!

 

[jrz126]

Looks like some pretty confusing logic there. Its been awhile since Ive dealt with VHDL.
I usually break this stuff down into smaller blocks. Seems like it would be easier to have a shift register that holds 6 bits of the data in, the output of the shift register is then fed into a comparator that compares it to 111000.