Library ieee;
use ieee.std_logic_1164.all;
Entity Decoder is
port(
d_in: in std_logic;
clk: in std_logic;
d_out: out std_logic_vector(31 downto 0)
);
end entity;
architecture behave of Decoder is
TYPE state_type is (sync_detecting,decoding);
signal state:state_type;
CONSTANT SYNC : std_logic_vector := "111000";
signal i : integer range 0 to 6;
BEGIN
process(clk,d_in)
variable sync_detected_n : std_logic;
Begin
if rising_edge(clk) then
case state is
when sync_detecting =>
sync_detected_n := '1';
i<=0;
sync_detection : while i<5 loop
if rising_edge(clk) then
if d_in = SYNC(i) then
i<=6;
else
i<=i+1;
end if;
if i=5 and d_in<=SYNC(i) then
sync_detected_n := '0';
end if;
end if;
exit sync_detection when i<=1;
end loop;
if sync_detected_n = '1' then
state<= sync_detecting;
else
state<= decoding;
end if;
When decoding=>
d_out<="11111111111111111111111111111111";
end case;
end if;
end process;
end;