Help with Frequency Reducer

I've made a frequency convertor which will reduce an input squarewave (of freq. 3 - 30 kHz, 50/50 duty cycle) by three (i.e. 1 - 10 kHz). This is done using a 7473 IC containing 2 J-K flip flops.

The problem is this: not only does the frequency reduce, but the duty cycle is now also reduced (33% high, 66% low). The circuit that this is going into in the next stage requires a 50/50 duty cycle.

Any ideas on what I'm doing wrong, or how to correct it? Sorry I haven't put any diagrams up but I've left them at work!

Thanks

I don't think you've done anything wrong, but you can fix the output at 50/50 duty using a 555 monostable, PROVIDING its not a changing frequency? Just attach the monostable to the output, and set the values so that its 50/50 duty with your frequency.

A one-shot (monostable) will only work at one frequency.

You can fix it if, as you say, your input duty cycle is symmetrical. See below. The only errors will be due to device propagation delays, which you can minimize if you need to by using fast parts.
That funny-looking gate is an exclusive OR. The flip-flops are D's. You can use JK's instead (with some modifications, of course).