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HEXFET avalanche rating

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Mosaic

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Hi All:
https://www.electro-tech-online.com/custompdfs/2013/01/44063.pdf

Ruggedized for avalanche.

I am using a bank of 6 of these Nfets in parallel driving a delta 20 Volt unipolar pulse @ 120Hz into a slightly inductive, capacitive load of around 8 mOhms DCR.
The simulation (Spice) shows about an 80 Amp kick back pulse as the NFets avalanche at 60V backemf.
The kickback pulse is 3uSecs long. or about .00033
My reading of the figure 14, Pulsewidth vs avalanche current, indicates that @ 3uSec and a sub .01 dutycycle , each NFET should handle a max. of 60 Amps repetitive avalanche pulsing. With 6 of the Nfets in the bank the load ought to share around 80/6 = 13 .4 Amps each give or take perhaps 50% based on individual avalanche behaviour.

I looked at snubbing but, is it necessary given the NFET avalanche ratings?
 
Avalancheing a mosfet is "safe" but causes HEAT.
80A x 60V =HEAT! I know the dutycycle is low but....
Please post your schematic.
 
Ok, i did some redesigning to avoid the avalanche, since slight differences in the pulse HEXfet bank could cause the HEXfet that avalanches first to be under duress.

Eventually had to dump about 1800 Amps using a pair of IRLB3036 driven by a series connected pair of 1.5KE18CA tranzorbs. The snubbing Nfets arallel pair causes the kickback pulse to be routed to the Source of the original Pulse bank.
The snubbing Vgs is protected by a 16V Zener (to ground) fed by a 5ohm from the 50V + triggering tranzorbs. Another 5 ohms in parallel with the 16V Zener and 5 ohm gate resistor grounds the tranzorbs for rapid turnoff of the gates (10 ohms to gnd).
The 1800 Amp snubbing pulse lasts about 1.5 uSec now. LTspice says the kickback is now 54V clamped. No avalanche in the original pulse bank. The 12V gate protection zener is seeing perhaps 350mA during the 1.5 usec pulse.
 
Most mos fet models don't do avalanche. Did you add a zener in your model or something.
It is hard to visualize your circuit from a description. A schematic is much better. The spice program is nice too.
 
Most mos fet models don't do avalanche. Did you add a zener in your model or something.
It is hard to visualize your circuit from a description. A schematic is much better. The spice program is nice too.
Most of the IR FETs with subcircuit models do model substrate diode breakdown. Of course, this doesn't necessarily mean they will survive it.
I have been playing with an IRF740 on my bench recently. It is avalanche-rated, breaking down at 400V. I haven't had a failure yet. I'm running at low duty cycle, because, as Ron Simpson noted, it generates a bunch of heat.
It's interesting that the subcircuit has 4 pins, so in LTspice, you have to use the NMOS4 symbol, but if you look at the subcircuit closely, substrate and source are tied to the same node (which has to be the case, because the device only has 3 pins). I guess you could modify the subcircuit if you wanted, and use the normal 3 pin NMOS symbol.
 
LTspice cct

Here is the simulation...remove the .txt extensions and place the .sub files in the lib/sub folder in LTspice.

The snubber is essentially an amplified (using Nfets) version of the 1.5KE18CA tranzorb.
 

Attachments

  • etocct.asc
    5.7 KB · Views: 157
  • 1.5KE18A.sub.txt
    970 bytes · Views: 168
  • irlb3036pbf.sub.txt
    1.9 KB · Views: 124
So are you just playing around or are you trying to charge a battery under controlled conditions?
If you are trying to get from 36 volts to 12 volts there are other ways to do this?
 
Hi, it's research into testing the rate of development of H & O gaseous nuclei formation due to electrolytic processes
 
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