Mosaic
Well-Known Member
Hi All:
https://www.electro-tech-online.com/custompdfs/2013/01/44063.pdf
Ruggedized for avalanche.
I am using a bank of 6 of these Nfets in parallel driving a delta 20 Volt unipolar pulse @ 120Hz into a slightly inductive, capacitive load of around 8 mOhms DCR.
The simulation (Spice) shows about an 80 Amp kick back pulse as the NFets avalanche at 60V backemf.
The kickback pulse is 3uSecs long. or about .00033
My reading of the figure 14, Pulsewidth vs avalanche current, indicates that @ 3uSec and a sub .01 dutycycle , each NFET should handle a max. of 60 Amps repetitive avalanche pulsing. With 6 of the Nfets in the bank the load ought to share around 80/6 = 13 .4 Amps each give or take perhaps 50% based on individual avalanche behaviour.
I looked at snubbing but, is it necessary given the NFET avalanche ratings?
https://www.electro-tech-online.com/custompdfs/2013/01/44063.pdf
Ruggedized for avalanche.
I am using a bank of 6 of these Nfets in parallel driving a delta 20 Volt unipolar pulse @ 120Hz into a slightly inductive, capacitive load of around 8 mOhms DCR.
The simulation (Spice) shows about an 80 Amp kick back pulse as the NFets avalanche at 60V backemf.
The kickback pulse is 3uSecs long. or about .00033
My reading of the figure 14, Pulsewidth vs avalanche current, indicates that @ 3uSec and a sub .01 dutycycle , each NFET should handle a max. of 60 Amps repetitive avalanche pulsing. With 6 of the Nfets in the bank the load ought to share around 80/6 = 13 .4 Amps each give or take perhaps 50% based on individual avalanche behaviour.
I looked at snubbing but, is it necessary given the NFET avalanche ratings?