Ok I'm obviously getting this all wrong. Back to basics, if an output equals 1 it means current has the potential to be drawn - is that correct? If so, using this diagram (which forms an AND gate)...
**broken link removed**
When A and B has a hypothetical input of 1, Q would output/equal 1; meaning current can be drawn - correct? - however, the first NAND gate should stop that because 1 + 1 = 0 so no current can flow ???
- Please bare-in-mind I am just starting logic gates and am a beginner -
- ...so could you explain in simple terms and try not to be too harsh
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