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Here I have designed a 4 bit adder circuit to breadboard. The amount of breadboards and components is not an issue, so I'm not too worried about the size. However, this is my first ever time designing a circuit/schematic so is there anything I can do to make the addition faster/more efficient or improve the circuit in any way? Also, is there any mistakes in my schematic? I have simulated it and it all seems to be working correctly. Just to clarify, you input a 4 bit number with the switches, then you set the number to memory location A with the PTM switch. It's then stored in four Flip Flops. Then you can switch to memory location B and repeat. Then 'read A' will input the number from memory A into the 4 bit adder, so will perform 'number A + 0', therefore just displaying A. Same goes for B, but if you activate both 'Read' switches it will add them and display the output of the 4 bit adder. First time posting, have done my best to read the rules but apologies if I've done something wrong! Thanks!
Eddie, a very nice circuit. I must admit I've only ever looked at building a discreet component math function at school, in practice its easier to us a micro. But its good to understand the process.
The one point I'd make about you're circuit is that the relay will probably need a series resistor.
If you want to increase the speed of the adder analogue circuits will be much much quicker.
It would be helpful if you could draw out the logic table for getting Q0 for example
You can eliminate the relays and the eight AND gates that feed into the S inputs of the flipflops, by making use of the flipflops' clock and D inputs. To do this, connect IN0 to the D inputs of the first flipflop in each bank, IN1 to the second flipflop in each bank and likewise with IN2 and IN3. Then, connect the Set A pushbutton to the clock inputs of the top row of flipflops, and the Set B pushbutton to the clock inputs of the bottom row of flipflops.
Relays require suppression diodes.
Bypass caps.
If CMOS remember to tie the unused inputs to the logic level resulting in the lowest power dissipation.
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