How to create a singular positive pulse signal

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Fluffyboii

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For a long time being unable to easily create a singular pulse, simulating something like a button press annoyed me. For example: I have two CD4017 chips in a sequencer. One of them is driving LEDs while other is used for logic signals. I did this because I did not want to bother with transistor buffers at each output. Both share same clock and reset inputs. But because we live an flawed World these chips are not in sync when the circuit is first powered on. LEDs and logic outputs don't match unless I give a positive reset signal at least for once. Even though this is not the end of the World it is very inconvenient. Yet I can't find a way to automate it.
Lets say I used the clock signal of the sequencer with a latch. Now I have a constant positive signal at latchs output. How will I make it a pulse though. Do I need another clock signal to pull the enable pin of the latch low, after that. Digially making this would require lots of work. In fact I already put more work into making two CD4017 work together inatead slapping some bjt buffers at the outputs already.

Or lets say I want a monolitic timer with NE555. But I want it to start as soon as when the circuit is powered on instead of connecting a button to trigger pin. There is no way of doing it as much as I know.

And while having the CS class about logic gates it always bothered me that there was not a clean way of having a "delay" gate of some kind. I mean you can use multiple gates and sequencal components to have the same effect but there are not a single prebuild, easy to apply delay option. Which usually makes things more complex than it should be.
I think some transistor magic should be able to create what I want. Sadly I can't wrap my head around analog mathematics rabbit hole. I can't do the calculations in order to design a realiable circuit lile that.
 
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Fluffyboii said:
I thought CD4017 worked fine with +12V reset signal. Was I doing wrong to connect positive rail to reset via a buton. Shall I use a 12V zener. I may have 9V zeners too.
Click to expand...

Calculate the ratio needed from supply specs in datasheet, then using that calc the zener
tolerance and see if its worst case min meets the min Vih spec for your calculation for the
12 V case.


Regards, Dana.
 
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Fluffyboii said:
I thought CD4017 worked fine with +12V reset signal.
Click to expand...
You are correct. The circuit in post #3 will not work with a CD4017.

To fix this, re-arrange the components. D1 and R1 go from the Reset input to GND, and C1 goes from the Reset input to Vcc. D1 remains pointed in the same direction - anode to GND, and cathode to the Reset input.

A problem with this circuit is that it works only if the 12 V source presents a relatively low impedance to GND when turned off. If not, such as the 12 V source is physically disconnected by a switch or circuit breaker, there is no low impedance path to discharge C1 so it is ready for the next power-on event.

One solution to fix this is to replace D1 with another resistor; we'll call it R2. Set R2 = 10 x R1. R2 provides a discharge path for C1 no matter what is happening on the 12 V rail. It also attenuates the amplitude of the Reset pulse by less than 10%, but this is well within the operating margins of a CMOS circuit running on 12 V.

For example, with:

C1 = 0.1 uF
R1 = 10 K
R2 = 100 K

the Reset pulse is approx. 1 ms, and the C1 discharge time is approx. 10 ms, plenty short enough to discharge C1 before the next power-on event. No opamps, gates, etc. needed. I don't know if this was stated before, but one R-C reset circuit can drive both 4017 Reset inputs directly.

ak
 
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The reset input to the 4017 is not schmidt triggered, so could cause
problems as Vcap hovers around threshold with noise present.


Regards, Dana.
 
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Disagree. It's the Reset input, not the clock or clock enable, and a power-on reset at that. If noise on the Reset input is interpreted as multiple transitions, so what? The internal flipflop stages have an asynchronous reset. As long as the input voltage level is solidly in the valid logical 1 range for a microsecond or more, and back to a logic 0 before the next clock edge, the chip will be completely reset every time.

With the circuit in #22, the chip is reset in less than 1 millisecond after power is applied. After 10 milliseconds, the Reset input is terminated to approx. 1.1 V through an impedance less than 10 K. It would take a noise spike of over 17 V on Vcc to cause an incorrect chip reset during normal operation. If that happens often enough to be a problem, you've got other problems.

ak
 
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Do we know precisely what the internal logic looks like ? And we have this for specs :



What happens when we violate that ?

Isn't it just good design practice to present logic with "clean" signals that meet specs ?


Regards, Dana.
 
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We know so little about how the logic was done internally so I still think "clean"
signals are good, or ones processed to be so.

But I have seen working mistakes, as well as ones that do not show up right away.

Just an advocate of recommending "clean" logic signals.

And I find it odd manufacturer saw fit to schmidt the clock input, assuming I gather
not needed on reset, yet was actual testing done to establish an unclean signal
was just fine on reset. Or was designer just limited in application experience.


Regards, Dana.
 
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Even if you get a "clean" reset to each 4017 doesn't necessarily mean they will be in sync. If a clock comes along at the same time the reset occurs then one might clock and the other might not. That's why I suggested holding in reset whatever generates the clock for a little longer than the 4017s.

Mike.
 
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Back to your original post, can be done easily with a ATTINY85, here is code to
do it. Can add code to it to detect supply V and trip sequence of reset and power
good from that. This is mBlock, you program in blocks and mBlock then converts to
Arduino code. That is followed by using an Arduino board, like Nano, to program an
ATTINY85. Could even code turning on power to other circuits, eg. make a power
sequencer using it.



ATTINY85 -



Regards, Dana.
 
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Then there is always do the power control and sequencer and wave generation on
one chip.....here two wavedacs shown, could have done 4. 16 bit sequencer, could
have done 32. Very little code for most of it required.







Note right hand window, top pic, lots of resources left for other uses.


Regards, Dana.
 

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danadak said:
Do we know precisely what the internal logic looks like ?
Click to expand...
Yes. All of the old 4000 series parts were documented down to the individual-transistor level back in the day.

danadak said:
View attachment 138631

What happens when we violate that ?
Click to expand...
If by "violate", you mean a reset pulse narrower than the stated minimums, then the part might not reset correctly.

BUT - That is not the case here.

The Reset input signal comes from an R-C exponential ramp, so there is no contact bounce on the leading and no contact grinding noise on the trailing edge. The only possible issue is a noise burst at the output of the first inverting stage in the Reset signal chain. This is possible because a CMOS inverter is in fact a high-gain linear amplifier that spends most of its life with the output saturated either high or low. There is a very narrow part of the input signal range that puts the output within its linear range. Across a few millivolts of input transition, the first stage output can be a linear noise burst. This noise burst is amplified by the next inverter in the signal chain, and the output is full-amplitude squarewave noise. That noise will do nothing.

Nothing, because the Reset signal does not clock a toggle flipflop or counter. It drives the *asynchronous* reset inputs of a group of five flipflops. After the first transition, whether from a super-clean source or a noise burst, the flipflops are reset. They just sit there no matter how often you bang on them, wide pulses, narrow pulses, whatever, Reset is reset. This is true for both the leading and trailing edges of the input reset signal.

Noise on a clock line and noise on a reset line are very different things. As long as the clock and enable inputs are stable, no amount of noise on the reset line can cause the part to un-reset (go to a non-0 state).

ak
 
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danadak said:
And I find it odd manufacturer saw fit to schmidt the clock input, assuming I gather
not needed on reset,
Click to expand...
Back in the 80's I asked Albert Medwin about this. It is not on the other inputs because the Schmitt input inverter was relatively expensive to produce. To see why, compare the internal schematic of a CD4049 or CD4069 with a CD40106. Even without the 106's output buffer stage, it is much more complex than the very basic 1960's circuit that was an internal component of every 400 series part.

And, as above, it was not needed for an async Reset input.

Most 4000 series clocked devices do not have a Schmitt circuit on any input. It was added to the 4017 clock input because the design team knew that because of its stepper nature, the part would have a mechanical switch as its clock input way more often that other parts. The clock input was designed specifically to debounce switch noise with a simple R-C circuit.

ak
 
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danadak said:
was actual testing done
Click to expand...
Among other things, RCA was developing CMOS circuits for an Air Force image processing system. Yes, these guys actually tested their parts.

danadak said:
Or was designer just limited in application experience.
Click to expand...
Really - ?

Consider the possibility that the same team that invented the CMOS Schmitt trigger input structure left it out of every flipflop Set and Reset input (and most counters and shift registers) in the 4000 series for a reason.

ak
 
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Among other things, RCA was developing CMOS circuits for an Air Force image processing system. Yes, these guys actually tested their parts.
Click to expand...

Actually as a production EE we did testing for mil that we did not do for commercial. I can also confirm
as a test engineer commercial grade parts not tested the same way. We generated code that left
out a lot of enhanced testing the mil guys would get, depending on part.

Consider the possibility that the same team that invented the CMOS Schmitt trigger input structure left it out of every flipflop Set and Reset input (and most counters and shift registers) in the 4000 series for a reason.
Click to expand...

In the 70's many chip designs done w/o field customer input. Read hi tech was learning how to interface
to customers, and it was an ongoing struggle between marketing and engineering. Humans learn very
slowly. In retro would be nice if many of these parts had better resiliency to noise and slow risetime inputs.

Regards, Dana.
 
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No doubt that was a consideration in metal gate CMOS, old geometries. Many parts were
compromises. One only has to look at many of the databooks of the era where variants
were done to save die area. Thank god, for the most part, that era is behind us.

Regards, Dana.
 
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CMOS gate gain, transition region :



HC Logic above. Gain of 10, so transition region wider than you suggest...more than a few mV.

Note some parts do have steeper transitions higher Gm mainly the buffers


And then we have the transition region current rise dumping noise onto Vdd and Vss. Further
aggravating transition eg, self generated noise. Not counting external noise on supply rails.



Regards, Dana
 
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Yes. All of the old 4000 series parts were documented down to the individual-transistor level back in the day.
Click to expand...

1983 RCA book shows some parts down to the transistor level, others like the 4017 no public
transistor level drawing I could find.



Regards, Dana.
 
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