P0 goes to a transparent latch(74xx373 or 74xx573), ALE goes to latch enable, Ground the Output Enable on the latch. Outputs of the latch go to A0 through A7 on the ROM. The 28C64 has 8K of space so you only five bits from Port 2. Connect P2.0 through P2.4 to A8 through A12. Ground the ROM Chip enable if there are no other external devices. Take the data lines from ROM and run them back to P0. D0 goes to P0.0 through D7 goes to P0.7
Assuming the hardware is configured correctly, you don't need to do anything special in the code. If you place variables or peripherals in external memory with the 'xdata' keyword available in many compilers(e.g. Kiel and IAR) then the compiler will generate the correct code.
One thing to remember about the 8051 architecture is that code space and data space are two different locations. Reading code space is done with the PSEN*(Program Store Enable*) signal. Reading data space is done with RD*(P3.7 on most 8051 variants), and writing data space is done with WR*(P3.6 on most 8051 variants)
Set your compiler up to have some variables in xdata space and write a small test program to read and write those variables. Tell the compiler to produce an assembly language listing and look at the compiled code. A read of a variable in xdata memory should look like:
Code:
mov DPTR,#xd_variable
movx A,@DPTR
It is the movx instruction, and only the movx instruction which activates the RD* control signal.
A write to a variable in xdata memory should look like
Code:
mov DPTR,#xd_variable
movx @DPTR,A
Again it is the movx instruction with the operands in the revers order that activates the WR* signal.
You said the part was an EEPROM. That means electrically eraseable to me. Do I understand that you intend to program the part while executing instructions from the part? If so you will net to use an 74xx08 AND gate to combine PSEN* and RD* and run it to the OE-bar pin on the 28C64. WR* can got the WE-bar pin on the 28C64. Remember also that a write to the part may take 10 milliseconds to complete, and I don't know if there are requirements for the timing of address and control signals during this time.