I need an explanation of circuit gain I'm seeing

[Trent]

I've been designing a simple dual FET Wheatstone bridge using the website "www.falstad.com/" which allows one to draw a circuit very easily and it shows how it runs and does all the calculations. It's very simple to use.

I've attached a pic of a typical circuit.

The transistors used in the simulation are supposed to be MPF102 n-JFETs, with Vp= -8V, and a 20mA limit.

By playing with bias resistor values, I've gotten some unusual results.

The attached graph and table of my data shows a range of values for FET gain, gm, and the signal amplitudes I got for each circuit I tried.

In the very high signal amplitude circuits, the resistor settings are extremely touchy. Small changes can send the amplitude from the mV range down to the uV range.

I thought gain above 5, or so, was not possible with FETs, so my questions are:

1. These high signal amplitudes don't seem possible, are they a fluke of the calculations?
2. Why should circuits with low FET gain, gm, have high signal amplitudes and vice-versa?
3. Why don't the circuits with the highest gm have the highest signal amplitudes?
4. Looking at the chart, which values should I strive for? High gm but lower signal amplitude (assuming these amplitudes are actually possible)? Or, low amplitude, with high gm value?
Or, should I look at some combination of the other FET parameters?

 

[audioguru]

Your schematic is a negative with a black background and it has dots all over the wires so it gives me the creeps. Why is it so odd??

A FET is far from being linear as you can see on the graphs. The specs of a FET are from poor to excellent and FETs having the same part number are very different.

 

[Trent]

The schematic is posted just as it is displayed on the simulation at www.falstad.com/.

I know FETs have specs that can vary all over, but this is a simulation, so they are identical all the time. The only FET spec I can alter is the Vp which I set for -8V corresponding to a MPF102 n-JFET.

There is nothing else in the circuit to adjust but voltage and bias.
FET stats are shown at bottom right.
The gm for the FET is in what I guess is the "normal" range of 2-4, so how can I get such a high ratio of signal out/signal in, yet at other times, I can have a low signal ratio while the FET gm is still "normal"?

I've included here the actual circuit schematic which gave me a signal ratio of 23.07, the highest I've gotten.

power=30V
Top resistors=9K each
Top 2 pots are each 1K with a 767 - 233 ohm split
FETs have a Vp = -8 V
Bottom pot in bridge is 10 ohms with 1 ohm jumpers on each half to keep resistance low but allow bridge output zeroing.
Last pot is 2K with a 1356 - 644 ohm split
Graphs show the input signal (1 mV) and the bridge output across the 10M resistor in the bridge (simulating a DVM)

When things are tweaked just right, the gain (signal out/signal in) is very high, though the calculated FET gain is in the normal range around 3 to 4. At these extremes, the bias resistor settings are very touchy. Sometimes just moving the pot one more "notch" on the simulation can send the output signal from the mV range down to the uV range. I'm wondering if maybe the high gains shown are just a fluke of working at these extremes. Maybe the calculations done by the website aren't completely accurate.