The schematic is posted just as it is displayed on the simulation at
www.falstad.com/.
I know FETs have specs that can vary all over, but this is a simulation, so they are identical all the time. The only FET spec I can alter is the Vp which I set for -8V corresponding to a MPF102 n-JFET.
There is nothing else in the circuit to adjust but voltage and bias.
FET stats are shown at bottom right.
The gm for the FET is in what I guess is the "normal" range of 2-4, so how can I get such a high ratio of signal out/signal in, yet at other times, I can have a low signal ratio while the FET gm is still "normal"?
I've included here the actual circuit schematic which gave me a signal ratio of 23.07, the highest I've gotten.
power=30V
Top resistors=9K each
Top 2 pots are each 1K with a 767 - 233 ohm split
FETs have a Vp = -8 V
Bottom pot in bridge is 10 ohms with 1 ohm jumpers on each half to keep resistance low but allow bridge output zeroing.
Last pot is 2K with a 1356 - 644 ohm split
Graphs show the input signal (1 mV) and the bridge output across the 10M resistor in the bridge (simulating a DVM)
When things are tweaked just right, the gain (signal out/signal in) is very high, though the calculated FET gain is in the normal range around 3 to 4. At these extremes, the bias resistor settings are very touchy. Sometimes just moving the pot one more "notch" on the simulation can send the output signal from the mV range down to the uV range. I'm wondering if maybe the high gains shown are just a fluke of working at these extremes. Maybe the calculations done by the website aren't completely accurate.