i2c tut

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Mosaic

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Can anyone point me to an i2c tut using the hardware of a 16F886 type chip? I am using asm
thx
 
Yes it is useful...but it doesn't mention how to address a larger eprom...that needs 2 address bytes.
 
You never mentioned e2proms in your original post, only that you were interested in the PIC hardware. For multi-byte addressable devices you will need to look at the manufacturers datasheets for the device you wish to program, in order to find out what is expected and then write your assembly routines to suit.

Incidentally, the link to the Microchip presentation document I gave you does actually "mention" how to send data to multi-byte addressable devices, specifically larger e2proms, beginning on page 23
 
Thanks, I figured it out after reading the complete doc.
The Eprom requires a Control byte (READ/WRITE) , 1 or 2 Address bytes and a data byte for writing.
Similarly it requires a Control byte for reading.

The part about entering write mode to set the address for read mode was a bit tricky but it works.

Interestingly this method is at odds with the 16f882 pdf which discusses no Control bytes but claims a control bit is part of the address byte, note figures 13-7 & 13-8 that use a 7 bit address and a 1 bit R/W flag. This 'bit' R/W method is echoed by the text Designing Embedded Systems with PIC microcontroller by Tim WilmsHurst on page 318. section 10.8.2.
 
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Yes it is useful...but it doesn't mention how to address a larger eprom...that needs 2 address bytes.
You mean an EEprom that has over 16k inside.... The two address bytes are for location within...

You can have my library if you want... also there is a software implementation in my tutorials, so you can see exactly what happens in the protocol...

The library includes an RTC single byte read / write as well....

The software version is in tutorial 6 the link's in my signature...
 

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I2C (or 2wire, depending on who you talk to) is one of those protocols that you will have an "aha" moment with. The control byte you refer to is always there, no matter what device you are talking to. The control byte contains the actual hardware address of the I2C device itself plus a R/W bit to signify reading from or writing to that device. In the case of an E2Prom, a 24C32 for example, there are 3 hardware address pins, the binary setting of which will determine the actual hardware address of the device. This hardware address allows multiple devices to all hang off the same I2C bus. In the case of the 24C32, you could potentially have 8 of these all hanging off the same I2C bus.
I suspect you are getting caught up in the language used by the different authors to describe the same thing, but I'm glad you got it working for you
 
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I got confused until I discovered that the first byte sent to the EPROM is a hard coded high nybble (hex A) as a control command and the low nybble consisting of a 3 bit address followed by a 1 bit R/W spec.. This isn't discussed on the i2c specification in the PIC datasheet which speaks of a 7 bit device address and a 1 bit R/W spec.

But onto another question: The 1,000,000 spec of erase/writes applies to each memory cell or the complete EPROM as a whole?
 
I think it refers to each memory cell?? It's the durability of the actual hardware... I use "Fram" this uses a different memory type and has 1 trillion erase/write cycles... It also has no write housekeeping so you can write immediately after a previous write..

The 3 bit device range address, is kinda standard.. I have seen several I2C devices that can be chained...
 
Yup, Ian is spot on, the erase/ write cycle specification is per cell rather than per device array. It's actually quite a common failure in equipment where the design/ application really calls for high yield, non volatile, memory but the low cost of the equipment forces the designer to look at less than ideal options
 
Cool, BTW is it reasonable to piggyback solder a second Eprom (SMD) onto the first (A0 hi) once I don't connect the 2nd device's A0,1,2 pins so as to end up with a device 0 & 1 for use?
 
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There are 8 devices within that address range... 8 x 256Kbit so you can piggyback two 1Mbit devices as long as A0 is high on one and low on the other... ( A 1Mbit device only has A0 that is useful..)
 
The idea is fine in theory, however, be careful of the devices you are using, read the datasheets for them before assuming they will work as you expect
As I remember, some devices allow the address pins to float and have internal pull-ups, so the address pins become high when left disconnected, while others have internal pull downs that will pull the address pin low when left unconnected. Earlier manufactured devices required to have the address pins either dynamically driven high or low or had to have their address pins tied to either vdd or vss.
 
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