Hi Ian,
I can't post the DSP Processor as it's company internal (developed here).
However, it has indeed 3 registers.
Interrupt Mask Register, which each bit of it enables / disables specific interrupt.
Interrupt Latch Register, which each bit of it latches / not latches specific interrupt (What does it mean Latching an interrupt?)
Interrupt Pending Register, which each bit of it specifies if specific interrupt is pending (or active) / not active.
I assume that the Pending Register is for a case where more than one interrupt occurs at the same time (or lower priority interrupt occur while ISR or higher priority interrupt is active), right?