Kerim
Member
Delta Sinewave Synthesis (DSS) belongs to the serial DAC family. It is based on the Delta Modulation (of its basic configuration).
The attached LTspice schematic is a simple Delta modulator of 1Vp sinewave and 1V pulse amplitude (usually, it is 5V from an MCU output pin).
An active low pass filter of 3rd order is added at its output.
The main two parameters on the schematic are (defined on the included text, SDM_tests_01.txt):
‘bits’ (the number of bits in one cycle of the sinewave)
i_step (the Delta step)
The other parameters are:
Np (the number of cycles to be modulated; Np=1 if ‘bits’ is even or Np=2 if bits is odd.
F_xtl (frequency of the MCU crystal).
cycles (MCU cycles of DSS loop, to be discussed later).
Fck (frequency of the Delta clock).
Fin (frequency of the audio sinewave to be modulated).
E (simulation end time).
Ne+1 (number of the sinewave cycles to be simulated).
S (start of sinewave cycle(s) to be plotted and could be saved as a ‘wav’ file).
Nn and Nh (number of harmonics for the FFT log to be generated by the '.four' command).
Notes:
[ 1 ]
About the command: .wave dlt0096_121u0.wav 8 2000K V(PLS)
If the '.wave' command is enabled, the generated Delta bits will be stored in an 8-bit wav file.
In the file name: ‘0096’ means ‘bits’=96 and ‘121u0’ means 'i_step'=121u.
[ 2 ]
SDM_tests_01.txt, that you can edit, is just a list of a few tests for different values of ‘bits’ and ‘i_step’.
The recommended range of 'bits' is from 96 to 3080 (this covers the high band of the audio spectrum)
In case there will be no one around here who has a reason to be interested in this sort of synthesis, I will not bother the forum with more details.
Kerim
The attached LTspice schematic is a simple Delta modulator of 1Vp sinewave and 1V pulse amplitude (usually, it is 5V from an MCU output pin).
An active low pass filter of 3rd order is added at its output.
The main two parameters on the schematic are (defined on the included text, SDM_tests_01.txt):
‘bits’ (the number of bits in one cycle of the sinewave)
i_step (the Delta step)
The other parameters are:
Np (the number of cycles to be modulated; Np=1 if ‘bits’ is even or Np=2 if bits is odd.
F_xtl (frequency of the MCU crystal).
cycles (MCU cycles of DSS loop, to be discussed later).
Fck (frequency of the Delta clock).
Fin (frequency of the audio sinewave to be modulated).
E (simulation end time).
Ne+1 (number of the sinewave cycles to be simulated).
S (start of sinewave cycle(s) to be plotted and could be saved as a ‘wav’ file).
Nn and Nh (number of harmonics for the FFT log to be generated by the '.four' command).
Notes:
[ 1 ]
About the command: .wave dlt0096_121u0.wav 8 2000K V(PLS)
If the '.wave' command is enabled, the generated Delta bits will be stored in an 8-bit wav file.
In the file name: ‘0096’ means ‘bits’=96 and ‘121u0’ means 'i_step'=121u.
[ 2 ]
SDM_tests_01.txt, that you can edit, is just a list of a few tests for different values of ‘bits’ and ‘i_step’.
The recommended range of 'bits' is from 96 to 3080 (this covers the high band of the audio spectrum)
In case there will be no one around here who has a reason to be interested in this sort of synthesis, I will not bother the forum with more details.
Kerim