Is unipolar PWM possible with a half bridge inverter?

Hi everyone,

I have designed and built a solar PV inverter. It works, but part of it isn't working quite as I intended. I'm hoping that someone can clarify something for me that would explain where I may (or may not) have gone slightly wrong.

I have a bipolar supply, producing 0, -V and V. That drives a half bridge; the idea is to use PWM to create a rough approximation to a sine wave on the output which is then filtered and put into a load (light bulb for now). I'm using a technique where the 50Hz (or 60Hz, whatever) sine wave is approximated using a sequence of 30 values: 0,0,1,0,1,1,1,1,1,1,1,1,0,1,0,0,0,-1,0,-1,-1,-1,-1,-1,-1,-1,-1,0,-1,0. Note there are three levels, 1 (output = V), -1 (output = -V) and 0 (output = 0). I believe the three level technique is called unipolar PWM.

My question is, is this actually achievable with a half bridge?

After looking at the waveform of the output of my inverter, below, I'm suspecting that for 0 output I actually need to switch the output to 0 and that this is different from having both upper and lower switches of the bridge turned off which I'm doing now. Where I'm presently turning both switches off the waveform is gradually decaying to 0 when I really want it to go immediately to 0. I can see how switching the output to zero would be possible with a full bridge (either both upper or both lower switches on) and that is indeed where I've seen all the references to unipolar and bipolar PWM.

I'm quite new to designing power electronics (and to this site) and any help would be appreciated. The only reference I could find in line with three level PWM was at
**broken link removed** where they talk about 'phase shedding', but I couldn't find a description of what that is. It may be irrelevant.

I hope I've adequately described the problem. There is much new terminology for me!

Here is a waveform of the output showing the 'decay' to 0 effect. I'm running at reduced voltage at present (it's safer, for now!). The good news is, the light bulb still glows, even if the waveform isn't ideal.

A schematic would sure help us understand what you are trying to do.

And the more we understand that, the better we can help you succeed.

Hi ChrisP58,

OK, here is a schematic of the circuit described above.

Re-wording it slightly the question is; with such a topology is unipolar PWM possible, or only bipolar PWM?

What are you using as a switch?
What value for L and C?
30 X 60hz=1800hz pwm frequency?
Your current is probably closer to what you want, but the voltage is not!
Your switch seems to open slowly.
What is between your computer and the switch.
In other words SEND MORE DATA.

Hello ronsimpson,

My question is a theoretical question regarding the topology shown. Discussing the choice of switching element is for example completely irrelevant at this level.

I tried to draw some red lines. Then the switch turns off the inductor should snap back. (flyback)
So either your switch turns off very slow or you don't have much current flowing or you have capacitors not show.
or ........
Another way to say it: If you have current flowing through a inductor then through a switch, when the switch opens up the voltage should jump to the other power supply.

Hi ronsimpson,

I think you might have misunderstood where the waveform is taken from; it's from the output, as in the voltage across the load. Sorry if that wasn't clear. I think what you are describing and have drawn in red is the voltage at the point between the two switches. As I understand it, at that point there will be fly-back action caused by the inductor, much as you have drawn.

Here is a waveform that I have drawn in blue showing the desired unipolar PWM output (across the load). I've been thinking about this problem a lot over the last couple of days and I am increasingly convinced that such output is not possible with a half bridge inverter. The V and -V output levels are possible, but generating the 0 level by turning off both switches is a problem (well unless L = 0, C = 0, and the load is purely resistive). I think one might be stuck with bipolar PWM output when using a half bridge. That is, V and -V are the only output levels possible. Alas bipolar PWM is less attractive due to the increased harmonics produced compared to unipolar PWM.



Or have I missed something?

Simulation shows the concept is ok :-
(Edit: s1 and s2 are merely switch control voltages used in the sim. S =1V = ON)

but generating the 0 level by turning off both switches is a problem

Click to expand...

Why? Catching diodes should suppress any back-emf spikes.

Hi alec_t,

Well that's pretty neat. Your simulation clearly shows unipolar output. This gives me hope! I'm going to see if I can run some of my own simulations; I had some kind of Spice simulation package on a PC many years ago but it never got reinstalled after upgrades.

I'm still wondering about the period during fly-back when both switches are off. There might be quite a lot of power dissipation in the diode during this period. Though that might be a limitation of the half bridge design itself. I need to keep reading.

Thanks for the enlightening simulation.

Martin v said:

There might be quite a lot of power dissipation in the diode during this period.

Click to expand...

Peak diode current is the current flowing in any inductive load at the moment of switch-off. Using a Schottky diode will minimise power lost in the diode. Most of the inductive energy should be dumped back into the supply.

If you add an extra switching element between the inductor input(bridge output) and ground that can be your 0 switch. The switch would need to be AC capable, i.e. two fets drain to drain, but then that is the same number of components as a full bridge.
The attached pdf shows a possible AC switch.

Hi moffy. Yes, both the twin FET idea and the AC switch sound like they would work (at least to me). I don't recall seeing any commercial inverters with that kind of output though so I'm wondering why. Maybe the drive circuit and power supply for the driver might result in quite a bit more circuitry (just wondering out loud here)? The full bridge seems to be the default go to solution that most everyone gravitates towards. I like the half bridge idea for its simplicity, as in half the number of switches.

I have come to the conclusion that having the 0 switch is likely to be important in a real world inverter. I have been working evenings on this all week and have one long message to post this weekend that explains my reasoning.

I have been further investigating three level PWM (unipolar PWM) using a half bridge, and thought I would document my findings here for anyone else who might happen down this curious path.

First of all, my conclusion is this. Using a half bridge three level (V, 0, -V) PWM is possible, however you may well be disappointed because while the half bridge can drive the output to V or -V, it cannot drive the output to 0 but has to let the output 'fall' to zero. This is a problem when a low pass filter is placed on the output of the bridge, as is commonly done in order to filter out higher harmonics (to reduce EMI). The result is that there is significantly more harmonic distortion in the output than you might expect. Ironic really as the reason for choosing three level PWM in the first place was likely to be to reduce distortion.

How I arrived at the conclusion follows (long).

I was impressed with alec_t's simulation, so thought I'd run some too. I went and downloaded a simulation package, LT Spice. In retrospect I should have been looking at simulations a lot earier. LT Spice is my new favourite package; it's awesome. I also found a good tutorial called **broken link removed** which is not too easy and not too hard.

To start with I put some real world values into alec_t's working simulation to see how things would look. This involved 325V for each rail (230VAC line output has 325V peaks), and changing the load to 100 Ohms (effectively my load as I hope to run four inverters into a single 2kW element (26 Ohm element) and each will see a quarter of that (100 = approx 4 x 26), I think...).

The low pass filter required some investigation. LC (12 dB/octave) filters seem to be almost universal on the output of mains inverters but I needed to figure out the cutoff frequency to use. I read somewhere that a good guideline is to choose the cutoff frequency to be logarithmically half way between the desired output freqency (line frequency, 50Hz) and the switching frequency. The switching frequency I'm using is 1500Hz (see original post, above) being 50Hz with 30 bits per cycle = 50 x 30 = 1500. So the logarithmic half way point, Fc = sqrt(f1 x f2) = 274Hz. A good starting point if nothing else. Filters have particular responses, described by the Q of the filter. I chose a filter with a Q of 0.5 (Linkwitz Riley response) because that is a low value for Q and low Qs don't have peaks. I thought peaks would be a bad idea. Q = 1/d and d is called the damping. C and L can be calculated as follows:

C = 1/(2 PI z d f) and L = z d / (2 PI f)

z is the impedance of the load, 100 Ohms in my case, assuming it is predominantly resistive. The result, C = 2.9uF and L = 116mH. I used these values in the simulations.

I was interested in looking at the total harmonic distortion (THD) of the output. Lower is of course better. For reference a square wave is a sine wave with 45% THD. Three level modified square wave can achieve as low as 23.8% THD depending on the pulse width (126.8 degrees of conduction time (out of 180 degrees) for a single pulse) is the optimal duration. The 30 bit magic power sine wave I'm using is theoretically around 12% (as long as you don't include hamonics above the 9th, where things get bad, hence the need for a low pass filter).

Some square wave, modified sine waveforms, as well as a diagram.

Incidentally, in LT Spice if you add the directive .fourier{freq} V(output) and another one .param freq 50 (for 50Hz - see my Spice file) you can perform THD analysis in LT Spice. You need to create an output label at the point you wish to measure the distortion. The results appear under View->SPICE Error Log after you have run the simulation.

Hint: under simulate->control panel, turn off 1st and 2nd order compression in order to improve (lower) the noise floor of fast fourier transfors (FFT) too.

I changed the simulation time window from displaying the first two cycles (0-40ms) to instead skip the first cycle and display 20-60ms. The filter isn't working at time=0 and by delaying for one cycle you make sure the filter is at its proper operating point for the first point displayed (or FFTed). This is actually quite important and if you don't get this right your distortion measurements will be probably not what you expect.

Initially I ran the 30-bit simulation with L = 0 and C = 0. THD 11.8%. Then I put in the chosen values of L and C. THD 25.1%. It actually increased! I would have expected a filter to reduce the harmonics, not increase them.

Half bridge, 30-bit waveform: L = 0, C = 0. THD 11.8%.
Half bridge, 30-bit waveform: L = 116mH, C = 2.9uF. THD 25.1%.

(I have attached the LT Spice files to this posting, so hopefully they too will appear somewhere, perhaps at the end of the post)

(also note, if you open each thumbnail in a separate tab on your browser it's easy to compare waveforms jst by flipping between tabs!)

I decided to simplify things and changed to a three level modified square wave with single pulses of 126.8 degrees duration.

Half bridge: L = 0, C = 0. THD 23.8%.
Half bridge: L = 116mH, C = 2.9uF. THD 18.0%


So for the traditional modified sine wave the filter reduced the THD (as expected).

I still had at the back of my mind the suspicion that the 0 level not being driven to 0 in the half bridge was causing a problem. If one looks carefully at the half bridge waveform you can see the issue. The voltage is not being pulled to 0 but to the opposite voltage due to the fly-back action (the yellow trace). At the output after the filter (blue trace), the slope of the curve is steeper in that part of the waveform than ideal.

As a comparison I decided to model the full bridge where 0 levels are actaully driven to 0. Notice that for L = 0, C = 0, the output THD is the same as for the half bridge. Putting in real values for L and C we see the THD for the full bridge drop significantly compared to the half bridge (12.0% vs 18.0%).

Full bridge: L = 0, C = 0. THD 23.8%.
Full bridge: L = 116mH, C = 2.9uF. THD 12.0%


This shows that if you are interested in the harmonics and the advantages that three level PWM (unipolar PWM) can provide, that you shouldn't be using a half bridge but something else that can drive to 0, like a full bridge.

For the sake of completeness I have simulated the 30-bit waveform running a full bridge:

Full bridge, 30-bit waveform: L = 0, C = 0. THD 11.8%.
Full bridge, 30-bit waveform: L = 116mH, C = 2.9uF. THD 4.9%.


With the 30-bit waveform in the case of the full bridge, we see the filter lowers the THD in stark contrast to the half bridge situation where it actually increases.

The upshot, I think I'll re-design my output stage to be a full bridge.

Nice analysis. Another convert to LTspice .
BTW, when using the .FOUR command, check that the frequency parameter is exactly the fundamental frequency your circuit is producing (e.g. it may be slightly shifted by adding filter components), otherwise the THD figures rise alarmingly.