Need an bit of help!
If the clock and data lines are both high the keyboard sends the (0) start bit, 8 data
bits, the parity bit and the stop bit. Data will be valid before the trailing edge and
beyond the leading edge of the clock pulse.
can any one explain this to me please?Does it mean that i need to capture the state of the data line when clock is high or when its low?
I'm now doing this:
If clock=0 Then ''when the keyboard wants to send data he pulls it to low level..
HSerout ["Data ready"] ''to debug console...
For bbit=0 to 10 '' 1 start bit, 8 data bits 1 par 1 stop bit...
last=1 ''security to captura data on seperate clock highs..??
While last=1 ''security to captura data on seperate clock highs..??
Delayus 4
If clock=1 then last=0
Wend
If ddata=0 then CLEARBIT vvalue,bbit
If ddata=1 then SETBIT vvalue,bbit
''HSerout ["Bit:",dec bbit,";",dec ddata," "]
Next bbit
HSerout ["RECV:",BIN VvAlue,10,13]
End if
When i hit an key on the keyboard i recieve Value 0! 2 times..
1 time because of making some key, another one because releasing some key...
now the trick should be that my timing or my scanning should be an bit better because in fact i never read ddata high...
Both Clock and Data are connected to 5volts with an 10K restitor like in the examples on the net.
what goes wrong??
Tks