KS0108 Reset Pin Question

I've built several successful applications using KS0108 based 64 x 128 pixel displays. In these applications I've tied the reset pin to Vdd.

The KS0108 documentation calls for a delay of 1 microsecond after Vdd is achieved before the reset pin goes high. It also call for for no more than 200 nanoseconds during which the reset pin climbs from 30% to 70% of Vdd. At least one fellow builder calls these requirements BS.

I'm working on an application that isn't (working.) I'm now down to timing issues as I'm convinced the data protocols are correct.

Is reset timing a valid concern? I'm reluctant to dedicate a PIC pin to the reset function. If necessary I'll create an RC delay circuit to drive a transistor that raises the reset pin after delay.

It could be the reset timing like that is needed on some displays and not others. The fact that a fast rise is asked for in the specification implies that more than one logic component inside the display is connected to the reset line.

You could try connecting a reset device to see if that gets your application working, or you could try different examples of the display.