Large C connected to CMOS Inputs

And where is that imaginary 3A going to?, it's yet another example of a wildly misleading simulation.

The chances of there being something on the CMOS power supply that can draw 3A is pretty remote, and even if there was, it would discharge the puny 0.1uF VERY rapidly.

It's a common issue, not because of imaginary high current's, but because power can feed in the I/O pin, through the top protection diode, and keeping the circuit powered up.

And where is that imaginary 3A going to?, it's yet another example of a wildly misleading simulation.

Click to expand...

The supply is not being disconnected in the sim, it is being reduced to 0V.......the charged cap
providing the current.....

The chances of there being something on the CMOS power supply that can draw 3A is pretty remote

Click to expand...

Load dependent .....

it would discharge the puny 0.1uF VERY rapidly

Click to expand...

"puny" you say, OK, puny for you. "VERY", excellent engineering characterization of RC decay.....NOT !

It's a common issue, not because of imaginary high current's, but because power can feed in the I/O pin, through the top protection diode, and keeping the circuit powered up.

Click to expand...

Thats the whole point of the sim, except source of current is cap which does NOT keep circuit
powered up.....

Another example of a wildly misleading response....

danadak said:

Folks seem to like building delays, debounce keys, etc, by placing large C at the
inputs to CMOS gates.

NOT A GOOD IDEA

For case where supply collapse rapid due to its design, load situation.

TI confirms this in an ap note on general CMOS usage. Here is a rough sim of the problem.
Note since spice model did not have the parasitic diodes in it I used external as substitute.
Also used 1 ohm as C ESR......roll your own value(s) for your case. Note using .1 ohms for
C ESR produced 3A thru D1......

View attachment 144963

The simple way around this is to place a series R between gate input and the large C.


Regards, Dana.

Click to expand...

I think your CMOS gate-equivalent circuit actually adds complexity and cannot be understood by the audience you've intended to inform. See post #2, for example.

danadak said:

The supply is not being disconnected in the sim, it is being reduced to 0V.......the charged cap
providing the current.....



Load dependent .....



"puny" you say, OK, puny for you. "VERY", excellent engineering characterization of RC decay.....NOT !



Thats the whole point of the sim, except source of current is cap which does NOT keep circuit
powered up.....

Another example of a wildly misleading response....

Click to expand...

In response to your usual 'chicken little' made up post to try and inspire fear!.

ZipZapOuch said:

I think your CMOS gate-equivalent circuit actually adds complexity and cannot be understood by the audience you've intended to inform. See post #2, for example.

Click to expand...

Ya, the two diodes (parasitic in all (almost all) CMOS) probably is too much, too challenging for some.

Chicken Little almost forgot to show what slow rise time signals at
CMOS inputs cause coupled with a little noise in system :




Stop the madness Chicken Little, just stop it.........

For thorough designers and engineers, just a refresher for you.......

Intermittent Vdd is a real life scenario with USB plugs and similar DC plugs and these transient DC sources are certain cause for concerns to CMOS SCR latchup in some cases.

This may or may not be the case with excess C applied to inputs. It all depends on the undocumented ESD protection designs in CMOS if they are single stage without R current limiting or the better dual stage cascaded diodes with R current limiting. I have long believed the latter to be the case since CMOS was first introduced with ESD protection. In this case the assertion made in this thread would be false.

But to be unsure we must assume the ESD protection design is true risk for C external energy to input until disproven.

Who has the facts on all NXP, TI, et al for EVERY CMOS logic ESD design?

The risk is that the ESD protection diodes could be fused open leaving the device exposed to interface cable handling exposures less protected. Or worse, contact bounce on inserting power with followon SCR latchup and with low 22 ohm ESR on 3.6V devices, subsequent thermal failure.

Ignoring the risk is ignorance.

e.g.

Image shown is a representation only. Exact specifications should be obtained from the product data sheet.




CD4049UB and CD4050B

This reminds me of the time when I had just finished a XY gantry using an Arduino Uno and CNC shield with CMOS to 3 FET FW bridge drivers hybrids.

When the 12V power source was unplugged, I was checking the stepper belt drive for drag and the mini 12V fan I added to the CNC shield started running slowly. That meant the Stepper motors were generating BEMF to 12V internal supply nodes from physical motion thru the ESD protection diodes to power the fan.

It worked but I stopped doing that test for reasons previously explained.

ESD Design Ref's


System Level ESD


p 146


ESD & EMI https://www.nxp.com/docs/en/application-note/AN10897.pdf
http://www.aecouncil.com/Papers/aec4.pdf Ford's photos of ESD damage

74HC looks like :



Yours, and some of my, words : Ignore at your own peril, NOT pontificate

Your post helpful, never looked at CD4000 way of doing it.

danadak said:

Folks seem to like building delays, debounce keys, etc, by placing large C at the
inputs to CMOS gates.

NOT A GOOD IDEA

For case where supply collapse rapid due to its design, load situation.

TI confirms this in an ap note on general CMOS usage. Here is a rough sim of the problem.
Note since spice model did not have the parasitic diodes in it I used external as substitute.
Also used 1 ohm as C ESR......roll your own value(s) for your case. Note using .1 ohms for
C ESR produced 3A thru D1......

View attachment 144963

The simple way around this is to place a series R between gate input and the large C.


Regards, Dana.

Click to expand...

Agreed this is a safer solution.

But the ESD diodes are much smaller Schottky devices with very low parasitic C and thus fairly high ESR (Rs) and thus current limit will be far less than 3A but could still exceed the 10 to 50 mA Absolute Maximum before fusing open. It all depends on the Joules of external capacitance vs the Joules of energy that can be dissipated internally before thermal failure.

All diodes in each family have a C*ESR or Rs*C = Tau constant and the Rs is inversely proportional to Pd max rating for ALL diodes. such that Rs* Pd max = k for k = 0.2 to 2 ( typ= 0.5 to 1). if k=1 this means a diode rated for 1 W has and Rs = 1ohm and for a <= 50 mW like ESD diode Rs >= 20 Ohms. The same is true for BJT transistors although deep trench ultra-low Rs transistors such as Diodes Inc/Fairchild designs will have low k ~ 0.2

In order to be faster than the CMOS logic FETs the parasitic C must be very low thus Rs is much higher than a 1N4148 100 mA Si diode (5 to 10 Ohms) yet Rs has a huge tolerance like hFE.

Here this this physics simulation shows the 1N4148 to rise 4V above 1V to 6A for Rs= 4/6= 667 mOhm thus with Pd = 500 mW max @ 175'C , k = 0.33 = 0.5W * 2/3 ohm,, C = 4 pF max , Rs*C= 8/3 ps
This neglects the NTC threshold shift lower from thermal rise and reverse recovery time mechanism.



Next a Schottky diode 2.9 Ohms nom. Rs bulk resistance 1N5711 . Pd max = 430 mW @ 150 'C Thus for k= 1, I expected Rs = 2.32 Ohms so k = 0.8 +/- wide tolerance.

Don't believe me, verify yourself as I have.

What is the minimum RC value to filter out switch bounce?
Answer= Double the bounce time

Let's say Bounce = 15 ms then if the Vih = Vdd/3 worst case, if closure to 0V bounces open the pullup threshold worst case minimum is only about half of the 63% exponential Tau = RC time constant so it must be doubled.

Thus RC must become 30 ms which could be 10 Meg pullup * 3 nF across contact to CMOS input.

Or 1 Meg || 30 nF or 100k|| 300 nF. From a point of view of noise immunity with switch on a long cable, one must consider ESD and EMF ingress crosstalk with the ratio of 100 pF human finger model for charge attenuation and add TVS for additional protect with an Rs current and ESD voltage limiting resistor.

The bottom line
Using excessively large caps for switch debounce is unnecessary and may exceed the absolute maximum diode input current rating on a dry contact power-up. The risk exists when the ESD protection limits are unclear for energy absorption in the ESD circuit. So do not always assume a pullup of 10k is needed for switch sensing and thus add 0.1 uF cap without a series Rs to the input.

Although assumed intuitive, let me say using a sensor switch to Vdd with a pull down resistor to 0V with a cap from Vdd to CMOS input is asking for SCR failures with intermittent contact power applied.

As a good engineering practice, I always include a BAT54S dual schottky on any input that has a C>0.1uf.

Tony Stewart said:

What is the minimum RC value to filter out switch bounce?
Answer= Double the bounce time

Let's say Bounce = 15 ms then if the Vih = Vdd/3 worst case, if closure to 0V bounces open the pullup threshold worst case minimum is only about half of the 63% exponential Tau = RC time constant so it must be doubled.

Thus RC must become 30 ms which could be 10 Meg pullup * 3 nF across contact to CMOS input.

Or 1 Meg || 30 nF or 100k|| 300 nF. From a point of view of noise immunity with switch on a long cable, one must consider ESD and EMF ingress crosstalk with the ratio of 100 pF human finger model for charge attenuation and add TVS for additional protect with an Rs current and ESD voltage limiting resistor.

The bottom line
Using excessively large caps for switch debounce is unnecessary and may exceed the absolute maximum diode input current rating on a dry contact power-up. The risk exists when the ESD protection limits are unclear for energy absorption in the ESD circuit. So do not always assume a pullup of 10k is needed for switch sensing and thus add 0.1 uF cap without a series Rs to the input.

Although assumed intuitive, let me say using a sensor switch to Vdd with a pull down resistor to 0V with a cap from Vdd to CMOS input is asking for SCR failures with intermittent contact power applied.

Click to expand...

I tend to base my answer on the fact that most humans are limited in their ability to push a switch a second time within 80mSec of the first. So, I want to debounce for 40 to 60 millisecond range which is way more than enough for a decent switch (even a really big bad toggle switch) to stop flapping.

If you really do the calculation, and determine how many time-constants you have as the voltage decays and the actual switching threshold of the hi-lo or low-hi transistion, you may have to include whether the switch normally high or normally low before the press and for the release and take the worst case scenario.

In any case, I normally error on the side of a second-press is not detected rather than a first press registers as multiple presses. Hopefully, you can find a happy medium without too much software overhead.

danadak said:

Folks seem to like building delays, debounce keys, etc, by placing large C at the
inputs to CMOS gates.

NOT A GOOD IDEA

For case where supply collapse rapid due to its design, load situation.

TI confirms this in an ap note on general CMOS usage. Here is a rough sim of the problem.
Note since spice model did not have the parasitic diodes in it I used external as substitute.
Also used 1 ohm as C ESR......roll your own value(s) for your case. Note using .1 ohms for
C ESR produced 3A thru D1......

View attachment 144963

The simple way around this is to place a series R between gate input and the large C.


Regards, Dana.

Click to expand...

Interesting...

1. I wonder if this is demonstrating why a buffered inverter (or non-schmitt input) shouldn't be used as an internal oscillation could occur as well (causing it to drawing more supply current)?

2. Could you sim the circuit after inverter power up with no inverter input. Then provide an input after a delay of a few milliseconds? I'd like to see the results please.

ZipZapOuch said:

I tend to base my answer on the fact that most humans are limited in their ability to push a switch a second time within 80mSec of the first. So, I want to debounce for 40 to 60 millisecond range which is way more than enough for a decent switch (even a really big bad toggle switch) to stop flapping.

Click to expand...

Good advice to limit the maximum toggle rate to effectively 15 to 20 pps without introducing false triggers or delays.

My main point is if the worst case threshold is half of tau @ 63% target that 2T is needed.
The other to minimize current.

The other issue might be current draw for upower coin-cell circuits because slow rising analog input can consume larger currents on the 74' CMOS series due to Pch-Nch crossover currents internally.

74HC02 for example

eTech said:

Interesting...

1. I wonder if this is demonstrating why a buffered inverter (or non-schmitt input) shouldn't be used as an internal oscillation could occur as well (causing it to drawing more supply current)?

2. Could you sim the circuit after inverter power up with no inverter input. Then provide an input after a delay of a few milliseconds? I'd like to see the results please.

Click to expand...

Basically 100 mS for power up and then input to inverter starts at 102mS, and output starts displaying at 110 mS :

danadak said:

Basically 100 mS for power up and then input to inverter starts at 102mS, and output starts displaying at 110 mS :

View attachment 144989

Click to expand...

Thanks.

Can you try the same using an unbuffered inverter 74HCU04?
If not, Ok. Just curious about the results.

eTech said:

Thanks.

Can you try the same using an unbuffered inverter 74HCU04?
If not, Ok. Just curious about the results.

Click to expand...

Got a behavioural model from TI, cant seem to get it to work or
make sense.

Regards, Dana.