First of all, I want to say I'm sorry for my impulsive edit earlier. I should have left the reply as it was initially.
I hope the next scheme will show off some progress in my understanding of transistors:
It is supposed to be a voltage gaining logical gate, fed by 7V. It's based upon two tutorials on amplifying:
this one and
this one. In my understanding the Voltage dividers (R1-R2 and R6-R7) are enhancing the input signal, while the ratio between R3-R4 and R8-R9 is important for the gain.
The scheme should block any output when either TORQUE or SIGNAL drops to (near) 0V. Though I'm affraid if Q1 does not conduct, current will flow through C2 and evantually reacht the CONTROLLER. If so, how to avoid this?
While both inputs provide current, CONTROLLER should receive a nice amount of Voltage (current is not needed too much). It can handle up to 5V (I'm curious what's going to happen when more is provided).
The precise values of resistors and capacitors is yet to be calculated. I now just copied the values of first tutorial.
Anybody any thoughts on this scheme? I'ld be pleased to hear them, and I sincerely hope this scheme starts making any sense...
Regards,
Mark