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jovabiot said:witch is the reason for explain that high and low level in a digital signalsare not the same?
Hmm ... I for one have no idea what you want to ask about. Please formulate your questions appropriately, preferably with more depth, to save on the huh-work around.jovabiot said:excuse me. The question is why the high and low level haven't the same time in some logic families??
not the rise and fall times, but the logic states at the output of a gate haven't the same time. if a introducy a clock siganl with a duty of 50%, at the output it isn't 50%.