logic states

J

jovabiot

New Member

• Jul 30, 2004

• #1

witch is the reason for explain that high and low level in a digital signalsare not the same?

 

Nigel Goodwin

Super Moderator

Most Helpful Member

• Jul 30, 2004

• #2

jovabiot said:

witch is the reason for explain that high and low level in a digital signalsare not the same?

Click to expand...

I don't really understand what you are asking?, but a digital signal is basically ON or OFF, a light switch is a good example.

 

G

grrr_arrghh

New Member

• Jul 30, 2004

• #3

are you asking why they are not the same? because if they were the same they would be useless...

 

C

checkmate

New Member

• Jul 30, 2004

• #4

Hmm ... is this a trick question?
Maybe because it is intentionally made different so that we can discern between them.

 

J

jovabiot

New Member

• Aug 1, 2004

• #5

excuse me

excuse me. The question is why the high and low level haven't the same time in some logic families??

 

Exo

Active Member

• Aug 1, 2004

• #6

time?

 

C

checkmate

New Member

• Aug 1, 2004

• #7

Re: excuse me

jovabiot said:

excuse me. The question is why the high and low level haven't the same time in some logic families??

Click to expand...

Hmm ... I for one have no idea what you want to ask about. Please formulate your questions appropriately, preferably with more depth, to save on the huh-work around.

 

G

grrr_arrghh

New Member

• Aug 1, 2004

• #8

also, if you could give specific examples, it would help.

Start from the start. Post your question again, and (as checkmate suggested) in as much detail as possible.

As you perhaps talking about the reaction times of various logic families?

 

J

jovabiot

New Member

• Aug 1, 2004

• #9

my problem is, that i introduce a digital signal of 20ns of time of bit in an inversor, and at the output the '1' is 18ns and the '0' 22ns, and alwais the ones are shorter then zeros. WHY??

 

Styx

Active Member

• Aug 1, 2004

• #10

ok well that gave me a head-ache reading that??

are you asking why a logic gate has a different rise-time to fall-time?

 

J

jovabiot

New Member

• Aug 1, 2004

• #11

not the rise and fall times, but the logic states at the output of a gate haven't the same time. if a introducy a clock siganl with a duty of 50%, at the output it isn't 50%.

 

samcheetah

New Member

• Aug 1, 2004

• #12

i think he is talking about gate propagation delay

this is common in digital circuits and certainly in logic ICs. there is a certain amount of time delay between the input and the output. this is due to the internal capacitance effects. and this cant be equal for two ICs of the same type and even for two signals.

why are u digging that deep. its only a difference of 4ns :lol:

 

samcheetah

New Member

• Aug 1, 2004

• #13

not the rise and fall times, but the logic states at the output of a gate haven't the same time. if a introducy a clock siganl with a duty of 50%, at the output it isn't 50%.

Click to expand...

thats also due to the internal defects of logic gate ICs

 

zevon8

New Member

• Aug 1, 2004

• #14

Its common in analogue circuits too. ie: Audio is delayed during processing in VCR's and TV's , but the video is not. Since the video signal path is longer than the audio path, a delay is required to "resync" the two at the output. For example, if it were not, the sound would appear before an actors lips moved, by just enough to be distracting.

This is actually an entire field of engineering almost on its own, since it has effects on all signal transfer, from telephone, to computers to wireless.

Not really your answer, but food for thought.