The feedback for the circuit you're asking about ( the one on the right ) is attained through the capacitor C2. Keep in mind that the common base amplifier is a low input impeadance one and is essentially driven by a current. So, as the voltage builds in the parallel RL circuit, C2 passes a current proportional to the RL circuit voltage and value of C2. That current is distrubited between RC, C1 and the Emitter of the transistor. Most of the current that enters the Emitter is output throught the Collector. Remember, the Common Base amplifier has high voltage gain, but less than unity current gain. However, large currents circulate through the LC network, and part of that is passed through the feedback capacitor, C2. In that way, the LC network can make up for the less than unity gain of the CB amp.
And so, oscillations will continue to build until the the trasistor's gain falls to a point where the total loop gain is less than unity. That ususally occurs near the cutoff or saturation region. From the bias arrangement, it appears that the gain drops while the transistor is near cutoff, at the lowest excursion of the signal.
If you digest all that, we can talk about the other circuit if you want.