LT SPICE AND gate??

I must be doing something wrong??
using an AND gate but two different inputs but same output??

LTSpice logic elements (inverters, buffers, gates, flops) are "idealized" (internal to LTSpice models of) logic elements, not like a specific logic family such as CMOS or TTL. They are optimized to simulate very fast, making simulations containing hundreds of them possible.

They operate on 1V.
They switch when an input crosses 0.5V.
They have an infinite input resistance ( ∞ fan-in).
They have an 1 Ω output impedance (almost ∞ fanout).
They have minimal switching delay, which can be modified on a per instance basis by attaching the Td=xxns attribute to the instance.

Look at the attached:
Note that the 10meg input resistor does not attenuate the input signal. Note that the gate switches as the input crosses 0.5V
Note that the output impedance at c and d is 1Ω, as shown when the gate is asked to drive a 10Ω resistor to ground or pulled up to 2V.

It's in the help file under Special Functions.

High and low voltages, rise and fall times, capacitance, impedence are all alterable on any particular instance or can be defined globally.