I think I may be ok, read post 18, it was a Mac issue. They hide the Library by default in Lion and Mountain Lion. Newest Software Releases. I'll let you know tonight when I get home if it works.
Thanks, Ron. Big Help. On my work Computer I was able to follow the correct path. I just don't have time to try it.
I attach all you need to SG3525A work in LTspice.
I also want to ask you, why you need MPK capacitor model? I doubt if we see any difference in simulation result. Simply use ideal cap.
How you going to model a ferrite core ?
I attach all you need to SG3525A work in LTspice.
I also want to ask you, why you need MPK capacitor model? I doubt if we see any difference in simulation result. Simply use ideal cap.
How you going to model a ferrite core ?
I was able to get it with your files the .asc it wasn't working until I pasted the .asc into .sym I thought the .asy was all I needed, and is the reason I couldn't get it to show up.
Ok, another question, this new LT Spice Model of the SG3525 has the pin location and are not in the same locations on the Data sheet? Can I just rename them? To a pattern closer to the original schematic or I just have to deal with it?
DataSheet.....https://www.st.com/web/en/resource/technical/document/datasheet/CD00000958.pdf
Ok, another question, this new LT Spice Model of the SG3525 has the pin location and are not in the same locations on the Data sheet? Can I just rename them? To a pattern closer to the original schematic or I just have to deal with it?
Pin location does not matter in spice. Only the pin name/function.
Even for schematic drawings, pins are usually placed by functional groupings that are often different than the location on the chip.
Pin location does not matter in spice. Only the pin name/function.
Even for schematic drawings, pins are usually placed by functional groupings that are often different than the location on the chip.
I have been working on the pin name and function, I hope I can jump my wires to get to the respective pins, that's if they will line up with the other schematic.
I don't know how to delete a wire connection in LT Spice yet
To start with just fill in the 'uF' part. If you want to get more accurate then work in the L and R part of the cap. Because this is not a low current timing cap don't worry about parallel resistance.
Look at the end of the data sheet at a graph called IMPEDANCE.
Look at a 1uF cap. There is a line starting high on the left and sloping down. This is what a 1uf cap should do. When the curve slopes up to the right this is what a inductor will do. Above 600khz the cap looks inductive. At 2mhz it is about 0.3 ohms. This gives us the inductance of the leads and connections inside the cap. (ESL) The resistance of the cap is 0.008ohms. (ESR) A perfect 1uF cap should have 0.01 ohms impedance at 2mhz but this cap will have 0.3 ohms. The real cap will have high frequency ripple, above 1mhz and a slight tendency to ring at 600khz.
When working with high current caps in power supplies the ESR and ESL makes the simulation more like the real world.
Thanks, Ron good explanation, I have to go to work now, it will take some time for me to consume what you said, but I got the last part of it. I'll try to apply it and get back to you.
As for my Core and windings of the GDT, I'm stuck again. I don't know how or what to do to make it work in the schematic.