LTspice hierarchical block

K

kingofjong

Member

• Jun 12, 2018

• #1

Hi

I am using LTspice to create a hierarchical block for a custom circuit. I keep getting the error



I tried debugging the problem and everything in the symbol seems correct. The symbol is associated with my schematic.



I also viewed the symbols netlist and got the error



I am not sure what I am doing wrong. I would appreciate any help.

Thanks

 

E

eTech

Well-Known Member

• Jun 12, 2018

• #2

Hi

Post the .asc and .asy tiles and we’ll take a look.

eT

 

K

kingofjong

Member

• Jun 15, 2018

• #3

Here is .asy and .asy

.asy



.asc and netlist



Thanks

 

DerStrom8

Super Moderator

• Jun 15, 2018

• #4

Your out1-out5 connections appear to not be connected. Note the electrical connection point on the left-hand side. There are no wires connecting to them.

 

E

eTech

Well-Known Member

• Jun 15, 2018

• #5

DerStrom8 is right.

You have the "out" labels at the left of the schematic disconnected. Mirror them so they will connected to the wires.

Also...
Remove "Memory" from the symbol "value" field until the schematic is converted to a .subckt file containing a "Memory" subckt definition.

eT

 

K

kingofjong

Member

• Jun 16, 2018

• #6

Thanks that fixed my unused port out issue.