To summarize this thread and make it easier for folks to take away useful info:
1) It turns out that FET matching seems
not to be the causative factor in random failure.
2) The devices were
exceeding the max SOA avalanche currents even though their temperature was managed, thus making for failure at some point.
3) A flywheel solution was
designed & tested which is capable of tolerating the >800A of peak flywheel currents and reverse load (battery) polarity.
4) Energy output of the Back EMF caused by parasitic inductance was quantified using capacitive storage capture of the energy which can be used to quantify the parasitic inductance.
5) A secondary effect of hi current switching transients hitting the FET gate via parasitic Cgd was looked at and no real benefit was found by attempting RC snubbing. Probably due to the fact that Cgd is over 1000pF on the IRFP3206. Reducing Gate Drive impedance helps somewhat, but gate transients may not be the problem here.
6) Thermal improvement (reduction) delta of 5X was achieved on the FET bank after snubbing the avalanche as indicated by FLIR camera monitoring.
7) Long term stability cannot be assessed at this time, but the SOA is now obtained on all parameters as the FETs have active thermistor feedback for current limiting.
Have a look at Table 2 in this doc for the parameters that matter when paralleling MOSFETs based on parameter importance:
https://www.infineon.com/dgdl/para.pdf?fileId=5546d462533600a401535744b4583f79
Thanks to all those who made suggestions. I feel much more confident going forward.