Mealy for 100101

Hi,
I am trying to work out a problem that is asking for a mealy machine that detects a pattern of 100101 and when it detects it, it continues to give an output of 1 till the system is reseted. I've trying a lot but when I simulate the results from the karnaugh maps I'm not getting the needed output at the specified instance. Does anybody know of some good place as I ve searched the net and didn't found any detection example for more than four bits. Names of good books are much appreciated.

thanks

trojsi said:

Hi,
I am trying to work out a problem that is asking for a mealy machine that detects a pattern of 100101 and when it detects it, it continues to give an output of 1 till the system is reseted. I've trying a lot but when I simulate the results from the karnaugh maps I'm not getting the needed output at the specified instance. Does anybody know of some good place as I ve searched the net and didn't found any detection example for more than four bits. Names of good books are much appreciated.

thanks

Click to expand...

hi troj,
Is the 100101 a serial or parallel string.??
Give us a little more detail.

In a communications system, a special header consisting of a bit stream 100101 is used to indicate a correct sequence. As soon as this sequence is received the circuit will stop and keep indicating that a correct sequence has been received and stay in that state till an asynchronous reset is received. Design a Mealy state machine to detect this sequence and thus indicate a correct start of sequence. Derive the logic equations using D and JK type flip flops. Which is the most compact solution? Does this always hold true?
After designing the circuit simulate it using Proteus to verify correct operation.

Hi,
I am assuming there is a Base clocking input for the 100101 bit stream.??

Look at this link example for a practical example.
**broken link removed**

Is there a clock with the data streem?
Is the data like this 0000101000000111100000(100101)000001000001000000111111111100000random
The output is like this 0000000000000000000000000000111111111111111111111111111111111reset000000

I referred to that link earlier but I had no luck, there seems to be quite a difference between a 4 bit and 6 bit recognizer, as 3 FF's are needed and to derive the state table its not that easy. I will attach some working I did and maybe someone can track any errors.

thanks

yes thats right .. that is what i want to see in the simulation.