Some considerations :
1) Input leakage I/O pin is 1 uA, but ADC input states input R is 100 Meg. Not exactly
clear whaich is dominant spec...but I will use 100M
2) Vref is ~ 10%, so lets use AVcc and a 5% or better regulator for chip Vcc. Double check reg used on board, its specs.
3) Max 9V duracell battery V, no actual spec but graphs seem to indicate 10V number safe.
4) So min Vcc on chip = Vref = 4.9V per NSP117 spec. Therefore divider must present from 10V a max of 4.9V.
Closest standard values would be 1 M ohm.
Witch respect to (1) above if leakage is dominant you would see an offset of 1 ua thru 1 M = 1 V,
so check with a DVM, just to make sure you do not have a large error term due to leakage. Do
this with just R2 in circuit.
For cap I would think .01 uF ceramic disk adequate.
Layout make divider close to chip, no long lead runs from battery to divider to minimize noise pickup.
Regards, Dana.