Microprocessor Theory Help Please

[dramrattan]

Consider a CPU with a 4MHz clock signal, connected to a 2MHz synchronous
bus. If we presume 1 machine cycle for each of the phases of the instruction cycle (fetch, indirect, execute, write) the instruction cycle will be 4 times as slow as the machine cycle. i.e. the maximum instruction execution frequency will be 1MHz. If instructions must be fetched across the bus, the minimum time in which an instruction fetch can occur (ignoring memory access timing) is 1MHz. This will not affect the instruction execution frequency if the processor is pipelined, but a non-pipelined processor will be slowed further to approximately 500kHz instruction execution frequency.

Hi i don't understand the bold statements. I understand pipeling is where the output of one stage is the input to the other so there's the overlapping effect in consecutive instruction cycles. The only way i could see they getting 500KHz instruction execution frequency slowing is by dividing 2MHz by four since its four phases for each instruction cycle right?...

But then that is saying each phase of the instruction cycle takes 2MHz to complete right?...Thus the machine cycle(machine cycle=bus speed???) is 2MHz and instruction cycle is 4 x 2Mhz since each instruction phase takes one machine cycle. So how in the world they get this statement "the MAXIMUM instruction execution frequency will be 1MHz.[/B] If instructions must be fetched across the bus, the MINIMUM time in which an instruction fetch can occur (ignoring memory access timing) is 1MHz?"

Sorry for the lenghty post & if i posted this in the wrong section.

Regards.

 

[dknguyen]

It's basically saying that it takes 4 CPU cycles to fully execute one instruction (one cycle for each of the four stages: fetch, indirect. execute, and write). Therefore a 4MHz processor can only execute a maximum of 1 million instructions as long as the memory is fast enough to keep up with no delays.

If you take into account memory accesses then the instructions and data can only be read and written to memory at the speed of the bus which is 2MHz (assuming the memory operates at the same speed as the bus or faster).

One Period of 4MHz = 250ns
One Period of 2MHz = 500ns

So for an instruction to execute each phase will take:
One 2MHz Bus Cycle (Fetch)
+ One 2MHz Bus Cycle (Indirect)
+ One 4MHz CPU Cycle (Execute)
+ One 2MHz Bus Cycle (Write)
------------------------------
500ns
+500ns
+250ns
+500ns
------------------------------
=1750ns period
=571428kHz frequency

If it took another 250ns (or 1 CPU cycle) then it would be 500kHz. I'm still trying to figure out what is eating up that time...It could be that since the clock of the bus is synchronous, it is always in synch with the CPU clock. So even though it only took 250ns for the CPU to "execute", it still has to wait another 250ns for the next edge of the BUs clock. That would make it 500kHz. Actually, I think that's probably what it is...

 

[dramrattan]

Thanks

Hi,

Thanks, you opened up my eyes with the detailed explanation of the instruction cycle on how long it takes to execute each phase. Damn you're good ...i would have never thought of that together with the explanation of the possible 500KHz delay due to synchronous timing.

Cheers!