Consider a CPU with a 4MHz clock signal, connected to a 2MHz synchronous
bus. If we presume 1 machine cycle for each of the phases of the instruction cycle (fetch, indirect, execute, write) the instruction cycle will be 4 times as slow as the machine cycle. i.e. the maximum instruction execution frequency will be 1MHz. If instructions must be fetched across the bus, the minimum time in which an instruction fetch can occur (ignoring memory access timing) is 1MHz. This will not affect the instruction execution frequency if the processor is pipelined, but a non-pipelined processor will be slowed further to approximately 500kHz instruction execution frequency.
Hi i don't understand the bold statements. I understand pipeling is where the output of one stage is the input to the other so there's the overlapping effect in consecutive instruction cycles. The only way i could see they getting 500KHz instruction execution frequency slowing is by dividing 2MHz by four since its four phases for each instruction cycle right?...
But then that is saying each phase of the instruction cycle takes 2MHz to complete right?...Thus the machine cycle(machine cycle=bus speed???) is 2MHz and instruction cycle is 4 x 2Mhz since each instruction phase takes one machine cycle. So how in the world they get this statement "the MAXIMUM instruction execution frequency will be 1MHz.[/B] If instructions must be fetched across the bus, the MINIMUM time in which an instruction fetch can occur (ignoring memory access timing) is 1MHz?"
Sorry for the lenghty post & if i posted this in the wrong section.
Regards.