I don't recognize your image source, but it contradicts the general wisdom of interface a uC to a FET but may be true for an open collector comparator with a pullup resistor and thus high impedance source. In the previous century, when CMOS 1st came out with 4xxx series devices the output impedance was generally high to prevent shootthru power dissipation thus ~ 1k @ 5V and ~ 300 ohms at 15V. So look at the emitter-follow (current amplifier) as an impedance reducer so output impedance of the emitter is Rout = Rin/ hFE , so if hFE =100 and Rin= 5k then Rout = 50 Ohms. But modern CMOS today has RdsOn of ~ 50 Ohms +/-25% typ. @ 5V and 74ALVxx CMOS like ARM's is rated for 3.6V and half the resistance of 74HCxxx family .
So the bottom line is that not only does it not help drive the FET due to the voltage drop of 0.7V , but it hurt the control of RdsOn of the FET by reducing the gate voltage called Vt or Vgs(th). This can range from 2 to 4V for older styles or higher voltage FETs or be <=1V for the "logic Level" type FETS which makes the transistors useless here as these were not available 40 yrs ago when your schematic image was probably created.
Conclusion: Consider that a history lesson and choose Logic Level FETs rated for at least 5x to 10x the current you intend to use and the Vdd you are using. if you want it cool. They usually specify RdsOn at -10% of common supply voltages. It is never used as a switch at Vgs(th) because that is just the threshold where it might conduct only 100 uA.
However your FET is only 5 mOhms and has a reverse capacitance of 58 pF typ. (Miller C) which means you can get glitches on the Vgs from flyback on the drain feedback. Often in half-bridge designs to prevent shoot thru, you must control Turn off faster than turn-on so diode R combinations. But a transistor could be used in this interface.
More specs are needed to choose the best topology.