Motorola 68hc11 assembly code (assignments/solved exercises)

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Microcontroller_fan

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Hey guys, nice to meet youI
I am learning assembly code and my teacher recommended me to start with this microcontroller.
The problem is that i was not able to find any solved assignments or exercises, i am a little confused (i am not an expert :/ ).
I want to improve my skills but i need some help, i cannot do it without a guide.

Could you please help me with some information or solved exercises about this microcontroller? I want to understand everything.
I want to be able to write programs using assembly code for this microcontroller.

Thanks!
 
To be honest, I don't think you've been given good advice. That is a very old processor and there are much better modern ones to work with. Most 16 or 18 series pic chips have everything built (including debugger) in so just the chip alone can be programmed. The above processor requires an external oscillator and, I think, some sort of monitor program. Here's a typical 68 evaluation board.

Mike.
 

Yeah, its pretty old but it is good for learning (i guess )
Dude, i want to learn assembly code using this microcontroller. Have you got any good guide about it?I want to see some good solved exercises, thats the best way.. i mean, i found a lot of information but i could not find solved exercises and thats the key
 
As you said, you can't find much about it. Try doing the same for pic chips and you'll be reading until next year.

Mike.
 
These are some fragments for one of our products that used a 68HC11F1 some years ago.
I can't give you the full file, but a few bits to get you started.
It's an assembler output listing so has the resulting machine code in the first couple of columns, where the source produces that.

First, the internal equates for the device registers, to be able to use those by name:

Code: 
                        *
1000                    REGISTER equ $1000 Default register set location
8000                    REG      equ $8000 Register base after remapping
                        *           
002C                    comminit equ %00101100  RX int, no TX interrupt, but tx and rx on 
                        *
0000                             org 0
                        *
0000                    PORTA    rmb 1 I/O port A
0001                    DDRA     rmb 1 Data Direction for port A
0002                    PORTG    rmb 1 I/O port G
0003                    DDRG     rmb 1 Data Direction for port G
0004                    PORTB    rmb 1 I/O port B
0005                    PORTF    rmb 1 I/O port F
0006                    PORTC    rmb 1 I/O port C
0007                    DDRC     rmb 1 Data direction for port C
0008                    PORTD    rmb 1 I/O port D
0009                    DDRD     rmb 1 Data direction for port D
000A                    PORTE    rmb 1 I/O port E
                        *
000B                    CFORC    rmb 1 Compare force reg.
000C                    OC1M     rmb 1 OC1 Action mask reg.
000D                    OC1D     rmb 1 OC1 Action data reg.
                        *
000E                    TCNT     rmb 2 Timer counter reg.
0010                    TIC1     rmb 2 Input capture 1 reg.
0012                    TIC2     rmb 2 Input capture 2 reg.
0014                    TIC3     rmb 2 Input capture 3 reg.
0016                    TOC1     rmb 2 Output compare 1 reg.
0018                    TOC2     rmb 2 Output compare 2 reg.
001A                    TOC3     rmb 2 Output compare 3 reg.
001C                    TOC4     rmb 2 Output compare 4 reg.
001E                    TOC5     rmb 2 Output compare 5 reg.
                        *
0020                    TCTL1    rmb 1 Timer control reg. 1
0021                    TCTL2    rmb 1 Timer control reg. 2
0022                    TMSK1    rmb 1 Timer interrupt mask reg. 1
0023                    TFLG1    rmb 1 Timer int. flags 1
0024                    TMSK2    rmb 1 Timer Int. mask reg. 2
0025                    TFLG2    rmb 1 Timer int. flags 2
0026                    PACTL    rmb 1 Pulse acc. control reg.
0027                    PACNT    rmb 1 Pulse acc. counter
                        *
0028                    SPCR     rmb 1 SPI Control reg.
0029                    SPSR     rmb 1 SPI status reg.
002A                    SPDR     rmb 1 SPI data reg.
                        *
002B                    BAUD     rmb 1 SCI Baud rate reg.
002C                    SCCR1    rmb 1 SCI Control reg. 1
002D                    SCCR2    rmb 1 SCI Control reg. 2
002E                    SCSR     rmb 1 SCI Status reg.
002F                    SCDR     rmb 1 SCI Data register.
                        *
0030                    ADCTL    rmb 1 ADC Control reg.
0031                    ADR1     rmb 1 A/D Result reg. 1
0032                    ADR2     rmb 1 A/D Result reg. 2
0033                    ADR3     rmb 1 A/D Result reg. 3
0034                    ADR4     rmb 1 A/D Result reg. 4
                        *
0035                    BPROT    rmb 1 EEPROM Block Protect Reg.
0036                             rmb 1 reserved
0037                             rmb 1 reserved
0038                    OPT2     rmb 1 System Configurations Options 2 Reg.
                        *
0039                    OPTION   rmb 1 System config. options
003A                    COPRST   rmb 1 Arm/Reset COP timer
003B                    PPROG    rmb 1 EEPROM programming control
003C                    HPRIO    rmb 1 Highest prio. int & misc.
003D                    INIT     rmb 1 RAM & I/O mapping reg.
003E                    TEST1    rmb 1 Factory test control reg.
003F                    CONFIG   rmb 1 COP, ROM & EEPROM enables.
                        *
0040                             rmb $1C reserved
                        *
005C                    CSSTRH   rmb 1 Chip Select Clock Stretch Reg.
005D                    CSCTL    rmb 1 Chip Select Control Register
005E                    CSGADR   rmb 1 General-Purpose Chip Select Address Reg.
005F                    CSGSIZ   rmb 1 General-Purpose Chip Select Size reg.
                        *
                        * End of Register block.
                        *
 
A few general equates, setting up other locations & storage:

Code: 
                        *
0000                    RAM      equ 0
                        *
                        *
0020                             org $20 Direct RAM
                        *
0020                    millisec rmb 1 Millisecond counter 0-9
0021                    hundsec  rmb 1 Hundredths second counter 0-9
0022                    tenthsec rmb 1 Tenths seconds counter
                        *
0023                    machtemp rmb 1 Temp. for re-arranged key sequence   
0024                    softkeys rmb 1 Switch input images
0025                    machkeys rmb 1
0026                    lastsoft rmb 1 Last time for change detect
0027                    lastmach rmb 1
0028                    newsoft  rmb 1 High for newly pressed sw.
0029                    newmach  rmb 1
002A                    softchar rmb 1 Key being repeated
002B                    machchar rmb 1
002C                    swchange rmb 1 Switch state changed flag
002D                    reptime  rmb 2 Repeat timer
                        *
002F                    brightns rmb 2 LCD Brightness store
0031                    contrast rmb 2 LCD Contrast store
 
Some startup code:

Code: 
                        * Start of program code:-
                        *
C000                             org $C000
                        *
C000 7E C0 03           RESET    jmp    start
                        *
                        *
C003 0F                 start    sei    disable ints.
C004 86 08                       lda    #$08 Set INIT register to map ram to 0000,
C006 B7 10 3D                    sta    REGISTER+INIT and register block to $8000.
C009 8E 3F F0                    lds    #$3FF0 Set stack pointer
                        *
                        * Setup I/O decodes and reset external devices
                        *
C00C 86 84                       lda    #$84        Set GP Decode address
C00E B7 80 5E                    sta    REG+CSGADR  to $84XX
C011 86 0E                       lda    #$0E        Set GP decode size
C013 B7 80 5F                    sta    REG+CSGSIZ  to 1K Byte
C016 86 00                       lda    #$00
C018 B7 80 5D                    sta    REG+CSCTL   Disable internal program & i/o decodes
C01B 86 04                       lda    #$04        Set GP decode stretch
C01D B7 80 5C                    sta    REG+CSSTRH  to 1 cycle
C020 86 80                       lda    #$80        Set options reg.
C022 B7 80 39                    sta    REG+OPTION  to turn on ADC
                        *
C025 86 00                       lda #$00
C027 B7 80 01                    sta REG+DDRA Set port A as all i/p (Softkeys)
                        * Port B = A8 - A15
                        * Port C = D0 - D7
                        * Port D = all o/p
C02A 86 FF                       lda #$FF
C02C B7 80 09                    sta REG+DDRD Set port D as all o/p
                        * Port E is input only. High bits = right machine keys
                        * Port F = A0 - A7
C02F 86 F0                       lda #$F0
C031 B7 80 03                    sta REG+DDRG Set port G as i/p on low bits (Left machine keys)
                        *
                        * Init timer for 1ms interrupts routine
                        *
C034 FC 80 0E                    ldd REG+TCNT
C037 83 03 E8                    subd #1000
C03A FD 80 16                    std REG+TOC1 Delay first compare as long as possible
C03D C3 03 DE                    addd #990
C040 FD 80 18                    std REG+TOC2
C043 86 FF                       lda #$FF
C045 B7 80 23                    sta REG+TFLG1 Reset any pending ints.
C048 86 C0                       lda #$C0
C04A B7 80 22                    sta REG+TMSK1 Enable OC1 interrupt.
                        *
                        *Set up o/p's for board functions         
                        *         
C04D 4F                          clra
C04E B7 84 41                    sta BDAC  Set DAC o/p to minimum
C051 B7 84 40                    sta CDAC
C054 B7 84 20                    sta LAMPS Turn off all lamps
C057 97 3F                       sta lampimg
C059 86 FF                       lda #$FF Set LCD control to black on white,
C05B B7 80 08                    sta REG+PORTD 40 col. mode
                        *
                        * Initialise memory locations
                        *
C05E CE 50 00                    ldx #RXBuffer
C061 DF 84                       stx rxbinp Set up buffer pointers
C063 DF 86                       stx rxbout
C065 CE 60 00                    ldx #TXBuffer
C068 DF 88                       stx txbinp
C06A DF 8A                       stx txbout
C06C CE 70 00                    ldx #ESCbuf
C06F DF 3B                       stx escinp
C071 DF 3D                       stx escout
C073 7F 00 3A                    clr escflag
C076 7F 00 2C                    clr swchange
C079 7F 00 26                    clr lastsoft
C07C 7F 00 27                    clr lastmach
C07F 7F 00 28                    clr newsoft
C082 7F 00 29                    clr newmach
C085 7F 00 95                    clr eptimer
C088 7F 00 94                    clr epdelay
                        *
                        * Clear scratchpad RAM
 
And the interrupt vector table that must be at the end of the address space:

Code: 
                        *
                        * Interrupt vectors
                        *
FFC0                             org $FFC0
FFC0 C9 59                       fdb dummyint Reserved              FFC0
FFC2 C9 59                       fdb dummyint Reserved              FFC2
FFC4 C9 59                       fdb dummyint Reserved              FFC4
FFC6 C9 59                       fdb dummyint Reserved              FFC6
FFC8 C9 59                       fdb dummyint Reserved              FFC8
FFCA C9 59                       fdb dummyint Reserved              FFCA
FFCC C9 59                       fdb dummyint Reserved              FFCC
FFCE C9 59                       fdb dummyint Reserved              FFCE
FFD0 C9 59                       fdb dummyint Reserved              FFD0
FFD2 C9 59                       fdb dummyint Reserved              FFD2
FFD4 C9 59                       fdb dummyint Reserved              FFD4   
FFD6 C8 48                       fdb COMMSINT SCI int.              FFD6
FFD8 C9 59                       fdb dummyint SPI int.              FFD8
FFDA C9 59                       fdb dummyint Pulse Acc input       FFDA
FFDC C9 59                       fdb dummyint Pulse Acc overflow    FFDC
FFDE C9 59                       fdb dummyint Timer overflow        FFDE
FFE0 C9 59                       fdb dummyint Output Compare 5:     FFE0
FFE2 C9 59                       fdb dummyint Output compare 4:     FFE2
FFE4 C9 59                       fdb dummyint Output compare 3:     FFE4
FFE6 C8 68                       fdb DISPINT  Output Compare 2:     FFE6
FFE8 C8 87                       fdb TIMERINT Output compare 1:     FFE8
FFEA C9 59                       fdb dummyint Input Capture #3:     FFEA
FFEC C9 59                       fdb dummyint Input Capture #2:     FFEC
FFEE C9 59                       fdb dummyint Input Capture #1:     FFEE
FFF0 C9 59                       fdb dummyint Real Time interrupt   FFF0
FFF2 C9 59                       fdb dummyint IRQ                   FFF2
FFF4 C9 59                       fdb dummyint XIRQ                  FFF4
FFF6 C9 59                       fdb dummyint SWI                   FFF6
FFF8 C9 59                       fdb dummyint Illegal Opcode        FFF8
FFFA C9 59                       fdb dummyint COP fail              FFFA
FFFC C9 59                       fdb dummyint Clock Monitor         FFFC
FFFE C0 00                       fdb RESET                          FFFE
                        *
                        *
                                 END
Errors: 0
 
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