Use falling-edge triggered D flip-flop(s) to design:
a. f/2 frequency divider for input frequency f
b. f/4 frequency divider for input frequency f
Draw waveforms to show operation of your circuits demonstrating appropriate frequency division.For the D flip-flops, if tsu=2ns, th=0ns, tC-Q=2ns, determine the highest frequency (f) of operation for your circuit. Will your circuit work if th=3ns instead of 0ns? If it doesn’t work, can you fix the problem without changing the flip-flop. You may change interconnect, add / remove gates, etc.
Determine the frequency for your modified circuit