You are absolutely correct about the OR gate. I smacked myself in the forehead this morning for not thinking of that earlier.
Thanks for the link. I have added a small delay for the FF clk input, Timer reset, and the gate check, which should allow for sufficient time for the states to be proper.
The way I've done the delay isn't the ideal way to do it, but was the only thing I could come up with, without using a timer. Assuming the internal resistance of the buffer is low compared to the resistors used-the initial delay on the reset is given by tOH = (R1C1+R2C2)*Ln[Vcc/(Vcc-vLH)], where R is resistance, C is the Capacitance, Vcc is the applied voltage in each stage, and vLH is the threshold voltage for the buffer (double inverter) to switch from low to high state. The on time of the delayed signal is given by tOL = R1C1*Ln{(Vcc/vHL)*[1-exp(-tp/R1C1)]} + R2C2*Ln{(Vcc/vHL)*[1-{(Vcc*vHL/[(Vcc-vLH)*(Vcc*{1-exp(-tp/R1C1)})])^(R1C1/R2C2)}*exp(-tp/R2C2)]} + tp - tOH, where tp is the pulse width of the original signal, and vHL is the threshold voltage for the buffer to switch from high to low state. This gives me a little bit of adjustment to delay a pulse with a certain output time. Of course, choosing RC too small, the delay will be too short (reseting the counter and shortening the incoming pulse, tp) or choosing RC too large will result in no output at all.
The point is, I was able to come up with suitable values for R's and C's. Assuming Vcc = 5V, vHL = vLH = 2.5 V, and tp = 1/(16X 9600[baud]), R1C1 =~ 3.5us and R2C2 =~3.5us (i.e approximately half the pulse width, which you probably could have guessed).
As can be seen in the attached picture, the reset pulse (11th clock of counter, shown in green) is delayed at the FF and Timer (shown in red). It can be seen that the Timer had not yet finished; the capcitor was prematurely discharged (yellow). The blue is another delayed signal from the FF Q' output, indicating the earliest time a signal from the timer is allowed to start the count sequence.