Need UART help

I’m a little confused on using a TL16C550C UART. It has a programmable baud rate generator, which must be initialized. I understand that this is done by choosing the Divisor Latch Register (through use of A0-A2 inputs and the DLAB in the line control register), but how do I write to the register when it doesn’t yet know the proper baud rate? Is there a default setting? I’m using a 1.8432 MHz clock. The same goes of the Line Control Register settings (word length, stop length, parity)-is there a default?

Also, I’m a little unsure if I’ve connected all the handshaking pins together correctly. I’ve used a null modem connection, but I’m not sure what to do with a couple of connections. I’ve seen the DCD connected either to RTS, DTR, or disconnected. Also, I assume I just leave the RI disconnected?


`PC_____UART
DCD <-- ?
RxD <-- Sout
TxD --> Sin
DTR --> DSR
`SG --- Vss (ground)
DSR <-- DTR
RTS --> CTS
CTS <-- RTS
`RI <--


Thanks for your help,
Sebastian

Hmm, I only skimmed over the datasheet....maybe I have missed something but surely you just set A2..A0 for the correct control register (BRG) then input your bytes throuhg D7..D0? Page 23 of the datasheet shows it.

With DLAB = 1, and A2,A1,A0 = 001 (upper byte of divisor) or 000 (lower byte of divisor) you can load in your two bytes for the divisor into D7..D0. I'm unsure of which 'CS' line to use but page 20 of teh datasheet looks like the basic setup.

As for the second question, I'm clueless, don't know much about null modems

Blueteeth

Oh, I was under the impression that I was supposed to use Sin from the PC to write to the Divisor Latch Register. If I'm to use D0-D7 however, how does the register know the beginning/end of what I am sending. Or am I supposed to set the pins D0-D7 and then change the register before disconnecting D0-D7?

I believe theres a timing diagram for just that in the datasheet. I would imagine, like most parallel interfaces, you set the A2-A0 as appropriate, then the D7-D0, and possibly the '/wr' line (pulled low). Then just toggle the CS line, and the whole thing is loaded in one go. Do this for the second byte of the divisor. As for 'begining/end', its parallel, so really there is not 'begining' or end. only a byte that gets loaded into the register location you determine with the A2-A0 lines.

I have to say it does look a bit convoluted to me, with all the register to set.

What application is this in? As in, what is controlling the UART chip..it IS a perihperal after all, not a stand-alone chip.

Blueteeth

Thank you, that makes a whole lot more sense now. Though, it looks like D7-D0 are written into the register whenever the write input is deactivated. It appears to be similar for reading. I wonder if this includes the Receiver Buffer Register. If so, that would seriously complicated what I want.

All that I am trying to do is to send a serial byte from my computer and turn it into parallel so that I can used it control another chip. I was hoping I wouldn't have to control the UART at all (except for the setup).

Then use a PIC, one chip and a little programming, that's all you need. For a hardware only solution use a 'real' hardware UART, the HD-6402 - but it's a multi-chip solution, as you require a clock generator.

Thanks, the HD-6402 looks a bit simpler to implement (PICs are a bit above my level for the moment). It looks like the HD-6402 doesn't have any modem handshaking business, or is this what I can use for the DRR input. As in, would I use the RTS (request to send) from the PC connected to the DRR (data received reset) on the UART to get it ready for the next data set? Or is there something else I'm supposed to use for DRR?

Mouser doesn't seem to have this UART and Digikey is out. Is there a similar place where I can purchase this, or a suitable replacement?

Thank you for your help.

ExtravDreams said:

Thanks, the HD-6402 looks a bit simpler to implement (PICs are a bit above my level for the moment). It looks like the HD-6402 doesn't have any modem handshaking business, or is this what I can use for the DRR input. As in, would I use the RTS (request to send) from the PC connected to the DRR (data received reset) on the UART to get it ready for the next data set? Or is there something else I'm supposed to use for DRR?

Mouser doesn't seem to have this UART and Digikey is out. Is there a similar place where I can purchase this, or a suitable replacement?

Click to expand...

All these types of chips are really old, but you're looking for an old solution.

Do you need handshaking?, what are you trying to do?.

No, I do not need handshaking, though it would be nice to know that it will always receive what I have sent. I think I could use the DR signal on the UART to CTS on the PC (making the appropriate level adjustments first), indicating the UART has a cleared buffer and can receive more data. But what can I use for the DRR input on the UART to clear the buffer? I can only think of dumb solutions such as, once the DR signal goes high (indicating the buffer is full), it starts a counter which after some short count cycle sends a signal to DRR. Any better solutions?

If you don't need handshaking, then why even consider it?.

Just to prevent overflow error. I'm trying to control several stepper motors on a rotational feedthrough. Essentially, I need very accurate movement and if I'm just sending commands without checking that they have been received, I won't be able to keep track of position. So, I don't need handshaking as long as I know the data has been received.

Any thoughts on what the input for DRR normally is?

I think I may just use a timer (555), triggered by the Serial data coming in, which will be active for the duration of the incoming data. I'll use the timer output to activate a frequency divider, which counts the UART clock. I may have to use another timer (triggered by the divider) to delay the reset, so that the first timer has already gone off by the time the next set of data comes in.

Any suggestions for an easy to use frequency divider? Any objections to SN54LS from TI other than it being over kill (and very expensive)? All I would really like is a programmable divider that allows selection from 1 to 4 stages. Maybe the CD4536B?

ExtravDreams said:

Just to prevent overflow error. I'm trying to control several stepper motors on a rotational feedthrough. Essentially, I need very accurate movement and if I'm just sending commands without checking that they have been received, I won't be able to keep track of position. So, I don't need handshaking as long as I know the data has been received.

Click to expand...

So you're just sending stepping patterns, with the speed of movement governed by how fast you send the data? - so there's no need (or use) for handshaking.

But really you shouldn't be using 30+ year old technology, a PIC would make this far easier, much cheaper, and more effective.

Well, sometimes I'll be taking upwards of 10,000 steps, so max speed without missing a step is necessary.

A PIC would be all those things if I knew anything about how to use one.

ExtravDreams said:

Well, sometimes I'll be taking upwards of 10,000 steps, so max speed without missing a step is necessary.

Click to expand...

Maximum speed is only very slow anyway, there's no processing time involved in the receiver, so how would it be possible to miss a step?.

So, I think this is what I'm going to do. Since the UART requires a RD input for the last data set stored in the buffer to be read at the D7-D0 outputs, I'm going to use a delay circuit, which is triggered by new incoming serial data.

I'm using a 555 Timer (in monostable mode), triggered by the Serial data (after conversion by Max232 to TTL lvl). The timer is setup for a minimum time until it may be triggered again, which is longer than 16 clocks at a low Baud rate. It will be reset at the 16th clock (or whatever will be appropriate) to allow the next serial data set to trigger the circuit again.

The Out of the timer goes through an AND gate, checking to make sure the Counter (a negative-edge triggered up-count frequency divider) is disabled and not currently in a count cycle. If so, it will trigger a toggle flip flop at the positive edge, enabling the count sequence. Once at the appropriate count (currently set to 14 by the gates at the Counter outputs) it will send a signal to the UART to output the data in its buffer at D7-D0. Then, 2 counts later, it will reset the Timer and the flip flop, allowing for the next data set.

The circuit I’ve drawn in CircuitMaker seems to work, until I have both inputs at the flip flop clk. For some reason, it doesn’t like the diodes there, which worries me a little bit.

You need a pull down resistor on the cathodes of your diodes. Why not just use an OR gate?
The circuit looks like it will be very metastable.
**broken link removed**

You are absolutely correct about the OR gate. I smacked myself in the forehead this morning for not thinking of that earlier.

Thanks for the link. I have added a small delay for the FF clk input, Timer reset, and the gate check, which should allow for sufficient time for the states to be proper.

The way I've done the delay isn't the ideal way to do it, but was the only thing I could come up with, without using a timer. Assuming the internal resistance of the buffer is low compared to the resistors used-the initial delay on the reset is given by tOH = (R1C1+R2C2)*Ln[Vcc/(Vcc-vLH)], where R is resistance, C is the Capacitance, Vcc is the applied voltage in each stage, and vLH is the threshold voltage for the buffer (double inverter) to switch from low to high state. The on time of the delayed signal is given by tOL = R1C1*Ln{(Vcc/vHL)*[1-exp(-tp/R1C1)]} + R2C2*Ln{(Vcc/vHL)*[1-{(Vcc*vHL/[(Vcc-vLH)*(Vcc*{1-exp(-tp/R1C1)})])^(R1C1/R2C2)}*exp(-tp/R2C2)]} + tp - tOH, where tp is the pulse width of the original signal, and vHL is the threshold voltage for the buffer to switch from high to low state. This gives me a little bit of adjustment to delay a pulse with a certain output time. Of course, choosing RC too small, the delay will be too short (reseting the counter and shortening the incoming pulse, tp) or choosing RC too large will result in no output at all.

The point is, I was able to come up with suitable values for R's and C's. Assuming Vcc = 5V, vHL = vLH = 2.5 V, and tp = 1/(16X 9600[baud]), R1C1 =~ 3.5us and R2C2 =~3.5us (i.e approximately half the pulse width, which you probably could have guessed).

As can be seen in the attached picture, the reset pulse (11th clock of counter, shown in green) is delayed at the FF and Timer (shown in red). It can be seen that the Timer had not yet finished; the capcitor was prematurely discharged (yellow). The blue is another delayed signal from the FF Q' output, indicating the earliest time a signal from the timer is allowed to start the count sequence.