New Spice model for CD4046B phase-locked loop IC.

alec_t

Well-Known Member

Most Helpful Member

• Sep 24, 2016

• #1

The current Yahoo LTspice User Group's model does not model the VCO section fully, so I home-brewed one which better reflects the functionality as set out in the Texas Instrument Application Report SCHA002A and the datasheet. I've uploaded the model and ancillary files to the User Group, but attach them here if anyone wants to play. Any bug reports gratefully received.

Edit: See post #9 and revised model posted there.

 

Attachments

• CD4046Bg.sub

  1.7 KB · Views: 2,579
• CD4046Bg.asy

  2.7 KB · Views: 2,516
• CD4046Bg-Test.asc

  2.5 KB · Views: 2,479

Last edited: Mar 6, 2018

Mikebits

Well-Known Member

• Sep 25, 2016

• #2

Very nice of you to share your work

 

alec_t

Well-Known Member

Most Helpful Member

• Sep 27, 2016

• #3

Thanks. Hope someone finds it useful.

 

T

Teleno

New Member

• Mar 2, 2018

• #4

alec_t said:

Thanks. Hope someone finds it useful.

Click to expand...

I do find it useful although I believe there's a bug: for some reason the PC2out is pulsing between Vdd/2 and Vss, not between Vdd and Vss as it should. I looked at the netlist but couldn't figure it out, perhaps you can take a look at it.

Thank you!

 

alec_t

Well-Known Member

Most Helpful Member

• Mar 2, 2018

• #5

Thanks for the bug report.
Here's what I get when I run the Test file I included in post #1.

Seems ok to me. Before lock is achieved the pulsing is 0V to 5V as expected. Whether the phase difference is positive or negative will determine whether the pulses are predominantly above or below the prevailing mean point. The PC2 output is a three-state one, so becomes biased at the capacitor voltage of the low-pass filter attached to PC2. This tends towards Vdd/2 as lock is approached.

[Edited]

 

Last edited: Mar 2, 2018

T

Teleno

New Member

• Mar 2, 2018

• #6

You're right, I misinterpreted the waveforms. Thanks for the clarification. Great model!

 

T

Teleno

New Member

• Mar 5, 2018

• #7

Yesterday I wired up a CD4046B on a breadboard to verify a simulation made with your model. The circuit didn't work, but it did when I inverted VCOout (after CompIn).
The same simulation using a 74HTC4046 model (file attached) produced the correct polarity of VCOout.
So I concluded that your model may need to invert the output VCOout and invert the input CompIn in order to match the component.

P.S. to use the 74HTC4046 model properly, you must define a parameter VCC, which this model uses for digital levels.

 

Attachments

• 74HCT4046.zip

  2.5 KB · Views: 1,162

alec_t

Well-Known Member

Most Helpful Member

• Mar 5, 2018

• #8

Thanks for that. Datasheets don't tell all. Nice to have it field tested, as I wasn't able to when I created the model. I'll look into it.

 

alec_t

Well-Known Member

Most Helpful Member

• Mar 6, 2018

• #9

Ok. Have modified the model as you suggested. Works ok in sim, but i'd appreciate it if you could compare its performance with the real IC and let me know the outcome.
Revised model attached.

 

Attachments

• CD4046Bg.sub

  1.7 KB · Views: 1,003

B

Brian802

New Member

• Aug 28, 2018

• #10

Thanks for improving this model. I need it to make an intelligent decision about the best phase comparator to use in my application... no time to get a PhD in PLLs!

I would like to use one of the higher frequency 4046-types, like the 74HCT4046 identified in message #7, which produces a third phase comparator output (R-S FF). Sadly, the model in the zip file says there is a problem interpreting the VCO input. Do you have the time to add the third phase comparator? I would be happy to validate it on the bench.

 

alec_t

Well-Known Member

Most Helpful Member

• Aug 28, 2018

• #11

Third comparator added.
Attached is my model of the CD74HC4046A, based on the somewhat skimpy TI datasheet and the 4046 model already posted. I'd be interested to know how it compares with the real world IC.

 

Attachments

• CD74HC4046Ag.sub

  1.7 KB · Views: 873
• CD74HC4046Ag.asy

  1.4 KB · Views: 863

B

Brian802

New Member

• Aug 28, 2018

• #12

Thanks, Alec. I will let you know how things work out on the bench.

 

M

Matthias Gebhard

New Member

• Oct 10, 2018

• #13

Thanks Alec!

 

M

maimci

New Member

• Nov 22, 2018

• #14

Hi Alec,
thanks for your interesting model. I think I found a possible bug however: it seems to me that there is a factor 10 on the center frequency, could it be? For example in my simulation I use R1=100k and C1=1n to lock a 1 kHz square wave, but according to the plots of revision of february 2003, with these values I should have roughly 50 kHz center frequency with Vdd=5V as I assume is in your model as you have a zener at the input. I attach the file, could you please check in what I am wrong? Thanks
maurizio

 

Attachments

• CD4046Bg-Test_2_mai.asc

  2.8 KB · Views: 676

alec_t

Well-Known Member

Most Helpful Member

• Nov 22, 2018

• #15

Well spotted. Thanks for the bug report. I'll look into it, but it may be a while before I can do that.

 

M

maimci

New Member

• Nov 22, 2018

• #16

alec_t said:

Well spotted. Thanks for the bug report. I'll look into it, but it may be a while before I can do that.

Click to expand...

Hi Alec,
thanks for quick reply. I did some further simulations and it seems that the factor is actually 2*pi, therefore what on the graphs is shown as Hz is rad/s on the simulation (therefore resulting in a lower frequency!). However at this point I do not know if it is a problem of the model or an error in the datasheet. The only way will be to test it on a real circuit but it will take for me a while before I can do that.
Regards
maurizio

 

alec_t

Well-Known Member

Most Helpful Member

• Nov 24, 2018

• #17

Have had a looksee.

maimci said:

in my simulation I use R1=100k and C1=1n to lock a 1 kHz square wave

Click to expand...

Did you have R2 connected when you ran your sim? If you make R2=R1=100k and C1=5n the PLL locks on to the 1.8kHz input of your posted .asc file ok when using the model you have. However, I agree the free-running f0 frequency is not what it should be, so I've modified the model and attached the new .sub file. This has improved things, but I'd appreciate a comparison with the real world circuit when you build it.
Incidentally, a good test for lock is to look at the voltage waveform on the LPF cap. It should show an oscillation which decays to a straight line as lock is approached.

 

Attachments

• CD4046Bg.sub

  1.8 KB · Views: 1,183

S

schmitt trigger

Well-Known Member

Most Helpful Member

• Nov 24, 2018

• #18

I am not at my desktop, will try your model when I fly back home ( with granddaughters now).

But anyway I can appreciate the effort you put here, and that you decided to share.

 

alec_t

Well-Known Member

Most Helpful Member

• Nov 25, 2018

• #19

The more I look at the App Note for the IC, the harder I find it to reconcile the VCO circuit it shows (Fig 8) with the values in the graphs (Figs 9a/b), so my model may still need tweaking.

 

M

maimci

New Member

• Dec 1, 2018

• #20

Dear Alec,
sorry for late reply, but it was a long week! Thanks for your updates. I am going to build a circuit in the next days and as long as I have the results I will let you know.
KR
maurizio