Could you please help me with this query? Thanks for the help!
I understand that when two or more open-collector gates are combined, you get a wired-AND gate. But such a wired-AND gates has negative logic which means it gives HIGH output only when all its inputs are LOW. I agree with the expression on the right which says X=A'B'C'D' where A' means complement of A.
I do not understand why the author is using uncomplemented inputs to derive output expression in subsequent sections. Please see the green highlights where it is said that X=ABCDEFGH and X=ABCDEF.
Is there a mistake in the text, or is it just me? Please guide me.
But I don't think that I understand it. The following picture is from the link provided by KeepItSimpleStupid . Both inputs should be LOW to get HIGH at the output X. This is open-collector AND gate. I'm sure that the missing of word 'wired' doesn't make much of a difference.
X = (Input_1)' (Input_2)' where apostrophe denotes complement.
Those are NAND gates, not AND gates. The dot / small circle on the output represents a signal inversion.
With both inputs connected together they function as simple inverters, with open collector outputs (though they are missing the OC symbol).
With that configuration, both gates need the inputs LOW to give high (open) outputs.
From the discussion, the following is what I have concluded. A wired-AND configuration of inverters is different from open-collector AND gate. A wired-AND configuration of inverters works like a negative-AND gate. An open-collector AND gate has a transistor attached to its output. Please have a look on the picture below. Do I have it correct?
I think. You are confused about a Low output being different than no output. In logic speak, a Low is literally a connection to ground. Several of your circuit images are directly connecting a low output to a high output which will short out the output pins and cause catistrophic damage to the component.
To be honest, there is still confusion in my mind and most of it comes from how the author has, in my opinion, mixed up the stuff in the given section. Anyway, let's see.
Yes, you are right. In open collector TTL inverter gate R3, Q4 and D2 are missing.
Do you really think that the circuit in FIGURE 2 is correct (Edit: FIGURE 2 from my previous post, post #8)? It says that a normal AND gate is connected to a normal inverter and then there is an open collector transistor attached to the output of inverter.
To get a NAND gate, as Nigel Goodwin pointed out, you can just connect an open collector transistor to the output of normal AND gate as shown below.
Do you really think that the circuit in FIGURE 2 is correct? It says that a normal AND gate is connected to a normal inverter and then there is an open collector transistor attached to the output of inverter.
To get a NAND gate, as @Nigel Goodwin pointed out, you can just connect an open collector transistor to the output of normal AND gate as shown below.
An AND gate connected to an inverter with an open collector output is functionally the same as an AND gate plus a transistor (which inverts) to give the open collector output. Each gives NAND function.
(Remember that in reality the external transistor would need resistors between gate & base and base-emitter.)
If the first text refers to an open collector AND, then the double inversion is correct, to retain the overall AND function.