operational-amplifier diff arrangement problem

[dark]

Hi ,
At the output of this ckt (attached) ,I see large common voltage , can I attenuate both channels with same ratio to reduce this. I need to interface this output diff signal to an IA which is powered by 5VDC , how to do this.

-D

 

[ericgibbs]

Hi ,
At the output of this ckt (attached) ,I see large common voltage , can I attenuate both channels with same ratio to reduce this. I need to interface this output diff signal to an IA which is powered by 5VDC , how to do this.

-D

hi,
If I follow you correctly.?
The cct you have posted is the front half of a 3 OPA IA, if you add the missing half ie: the 3rd opa, the output will have the CMV cancelled.
So a standard OPA powered by 5V would be acceptable when connected to the output of the 3rd OPA.

 

[crutschow]

As Eric noted, that schematic appears to show two op-amps of a three op amp differential instrumentation amp. You can make a two op-amp differential circuit (EDN PDF), but their performance is not as good as the three op-amp circuit and their minimum gain is 2.

 

[dark]

Thanks for the replies , The schematic I show is buffering differential signal which has a 12V as Vcc . The RHS of the circuit requires an interface to 5V powered subsystem ,say for example a diff-Adc (not SAR-ADC) . Now the signal looks like having un-tollerable CMV for this type of interface , I was thinking if we attenuate both channels independantly with a ratio of 2:1 , is this an applicable solution .

 

[crutschow]

Thanks for the replies , The schematic I show is buffering differential signal which has a 12V as Vcc . The RHS of the circuit requires an interface to 5V powered subsystem ,say for example a diff-Adc (not SAR-ADC) . Now the signal looks like having un-tollerable CMV for this type of interface , I was thinking if we attenuate both channels independantly with a ratio of 2:1 , is this an applicable solution .

You can do that but, of course, it will attenuate the signal you want also.

Instead why not use a fully-differential I/O op amp designed for this purpose such as these Operational Amplifier (Op Amp) - Fully Differential Amplifier - THS4151 - TI.com.

 

[dark]

Thanks for the reply , I just see my ADC specs says:



130dB CMRR , which resolves to 1.8uV signal at output for 6V common mode signal . Am I still missing the point?


Regards
-D

 

[ericgibbs]

Thanks for the reply , I just see my ADC specs says:

130dB CMRR , which resolves to 1.8uV signal at output for 6V common mode signal . Am I still missing the point?


Regards
-D

hi,
Looking at your original circuit and its output voltages, the differential of the two outputs is about 5 or 6volts.

This will be 'seen' by the ADC input as a differential signal, NOT a common mode signal.

Can you give us more detail regarding the actual signal source.??

 

[ericgibbs]

hi,
Looking at your original circuit and its output voltages, the differential of the two outputs is about 5 or 6volts.

This will be 'seen' by the ADC input as a differential signal, NOT a common mode signal.

Can you give us more detail regarding the actual signal source.??

hi,
This is your org circuit using LTspice.

 

[dark]

hi,
Looking at your original circuit and its output voltages, the differential of the two outputs is about 5 or 6volts.

This will be 'seen' by the ADC input as a differential signal, NOT a common mode signal.

Can you give us more detail regarding the actual signal source.??

Hi ,

Thanks for the simulation , actually this 8.4V signal will be seen by +IN pin and spec is asking for Vcc+.3Vmax . Will CMRR help here .

Regards

 

[ericgibbs]

Hi ,

Thanks for the simulation , actually this 8.4V signal will be seen by +IN pin and spec is asking for Vcc+.3Vmax . Will CMRR help here .

Regards

hi,
The CMRR refers to the 'dc' component of the input signal, not the difference signal applied to the two input pins of the IA.

It would help if you posted a full circuit showing what voltages are being applied to the IA and the expected diff signal input range, also what signal levels you are expecting at the input of the ADC.

Need more information..

 

[dark]

hi,
The CMRR refers to the 'dc' component of the input signal, not the difference signal applied to the two input pins of the IA.

It would help if you posted a full circuit showing what voltages are being applied to the IA and the expected diff signal input range, also what signal levels you are expecting at the input of the ADC.

Need more information..

Hi , I feel there is some confusion yes spec says absolute/common mode voltage DC to be below Vcc+.3V each pin .I attach a file showing 'z'=zero scale , 'FS'=full scale Please find below;

Rgds

 

[ericgibbs]

Hi , I feel there is some confusion yes spec says absolute/common mode voltage DC to be below Vcc+.3V each pin .I attach a file showing 'z'=zero scale , 'FS'=full scale Please find below;


Rgds

hi,
Just to confirm, looking at your last diagram.

You state that for the input to the OPA that the ZERO state is V=5.77477 on BOTH input pins and that the FULL SCALE differential input is V=5.7405 and V=5.67196

This suggests that the differential input signal is unipolar in sense and not bipolar, is this correct.?

If yes, then by using a standard 3 * opa IA, the output from the IA would always be unipolar in sense and the CMV cancelled.???

I see that you are using a differential input 24bit ADC with a SIGN bit to indicate input signal polarity.

As described above the ADC digitised output, assuming Vref for the ADC is 0.5*Vcc, would always be above the centre bit pattern, say positive.

Is this correct sofar.?

 

[dark]

hi,
Just to confirm, looking at your last diagram.

You state that for the input to the OPA that the ZERO state is V=5.77477 on BOTH input pins and that the FULL SCALE differential input is V=5.7405 and V=5.67196

This suggests that the differential input signal is unipolar in sense and not bipolar, is this correct.?

If yes, then by using a standard 3 * opa IA, the output from the IA would always be unipolar in sense and the CMV cancelled.???

I see that you are using a differential input 24bit ADC with a SIGN bit to indicate input signal polarity.

As described above the ADC digitised output, assuming Vref for the ADC is 0.5*Vcc, would always be above the centre bit pattern, say positive.

Is this correct sofar.?

Hi,
Yes , its correct .

Regards

 

[ericgibbs]

Hi,
Yes , its correct .

Regards

hi,
This is one option that could be used.
Use the unipolar output from the IA into one pin of the ADC and set the other input pin of the ADC to the 1.4Vref as shown on these sims.

 

[dark]

Hi,
Thanks for the simulations! ,could there be a method for true differential measurement .



Regards
Adi